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[/] [oms8051mini/] [trunk/] [rtl/] [core/] [digital_core.v] - Rev 6
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////////////////////////////////////////////////////////////////////// //// //// //// OMS 8051 Dgital core Module //// //// //// //// This file is part of the OMS 8051 cores project //// //// http://www.opencores.org/cores/oms8051mini/ //// //// //// //// Description //// //// OMS 8051 definitions. //// //// //// //// To Do: //// //// nothing //// //// //// //// Author(s): //// //// - Dinesh Annayya, dinesha@opencores.org //// //// //// //// Revision : Nov 26, 2016 //// //// //// ////////////////////////////////////////////////////////////////////// // v0 - Dinesh A, 26th Nov 2016 // 1. MAC related logic are remved ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// `include "top_defines.v" module digital_core ( reset_n , scan_mode , scan_enable , fastsim_mode , mastermode , xtal_clk , clkout , reset_out_n , // Reg Bus Interface Signal ext_reg_cs , ext_reg_tid , ext_reg_wr , ext_reg_addr , ext_reg_wdata , ext_reg_be , // Outputs ext_reg_rdata , ext_reg_ack , // UART Line Interface si , so , spi_sck , spi_so , spi_si , spi_cs_n , // External ROM interface wb_xrom_adr , wb_xrom_ack , wb_xrom_err , wb_xrom_wr , wb_xrom_rdata , wb_xrom_wdata , wb_xrom_stb , wb_xrom_cyc , // External RAM interface wb_xram_adr , wb_xram_ack , wb_xram_err , wb_xram_wr , wb_xram_be , wb_xram_rdata , wb_xram_wdata , wb_xram_stb , wb_xram_cyc, ea_in ); //---------------------------------------- // Global Clock Defination //---------------------------------------- input reset_n ; // Active Low Reset input scan_mode ; // scan mode input scan_enable ; // scan enable input fastsim_mode ; // Fast Sim Mode input mastermode ; // 1 : Risc master mode input xtal_clk ; // xtal clock 25Mhz output clkout ; // clock output output reset_out_n ; // clock output //--------------------------------- // Reg Bus Interface Signal //--------------------------------- input ext_reg_cs ; input ext_reg_wr ; input [3:0] ext_reg_tid ; input [14:0] ext_reg_addr ; input [31:0] ext_reg_wdata ; input [3:0] ext_reg_be ; // Outputs output [31:0] ext_reg_rdata ; output ext_reg_ack ; //---------------------------------------- // UART Line Interface //---------------------------------------- input si ; // serial in output so ; // serial out //---------------------------------------- // SPI Line Interface //---------------------------------------- output spi_sck ; // clock output spi_so ; // data out input spi_si ; // data in output [3:0] spi_cs_n ; // chip select //---------------------------------------- // 8051 core ROM related signals //--------------------------------------- output [15:0] wb_xrom_adr ; // instruction address input wb_xrom_ack ; // instruction acknowlage output wb_xrom_err ; // instruction error output wb_xrom_wr ; // instruction error input [31:0] wb_xrom_rdata ; // rom data input output [31:0] wb_xrom_wdata ; // rom data input output wb_xrom_stb ; // instruction strobe output wb_xrom_cyc ; // instruction cycle //---------------------------------------- // 8051 core RAM related signals //--------------------------------------- output [15:0] wb_xram_adr ; // data-ram address input wb_xram_ack ; // data-ram acknowlage output wb_xram_err ; // data-ram error output wb_xram_wr ; // data-ram error output [3:0] wb_xram_be ; // Byte enable input [31:0] wb_xram_rdata ; // ram data input output [31:0] wb_xram_wdata ; // ram data input output wb_xram_stb ; // data-ram strobe output wb_xram_cyc ; // data-ram cycle input ea_in ; // input for external access (ea signal) // ea=0 program is in external rom // ea=1 program is in internal rom //--------------------------------------------- // 8051 Instruction ROM interface //--------------------------------------------- wire [15:0] wbi_risc_adr; wire [31:0] wbi_risc_rdata; //----------------------------- // wire Decleration //----------------------------- wire gen_resetn ; //--------------------------------------------- // 8051 Instruction RAM interface //--------------------------------------------- wire [15:0] wbd_risc_adr ; wire [7:0] wbd_risc_rdata ; wire [7:0] wbd_risc_wdata ; wire [14:0] reg_uart_addr ; wire [31:0] reg_uart_wdata ; wire [3:0] reg_uart_be ; wire [31:0] reg_uart_rdata ; wire reg_uart_ack ; wire [14:0] reg_spi_addr ; wire [31:0] reg_spi_wdata ; wire [3:0] reg_spi_be ; wire [31:0] reg_spi_rdata ; wire reg_spi_ack ; wire [3:0] wb_xrom_be ; wire [3:0] wb_xram_be ; wire [7:0] p0 ; wire [7:0] p1 ; wire [7:0] p2 ; wire [7:0] p3 ; wire [31:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata : (reg_spi_ack) ? reg_spi_rdata : 'h0; wire reg_ack = reg_uart_ack | reg_spi_ack; assign reset_out_n = gen_resetn; assign wb_xram_adr[15] = 0; assign wb_xram_adr[1:0] = 2'b00; assign wb_xrom_adr[15:13] = 0; wire [9:0] cfg_tx_buf_qbase_addr; wire [9:0] cfg_rx_buf_qbase_addr; assign reg_uart_addr[1:0] = 2'b0; assign reg_spi_addr[1:0] = 2'b0; //------------------------------------------- // clock-gen instantiation //------------------------------------------- clkgen u_clkgen ( . reset_n (reset_n ), . fastsim_mode (fastsim_mode ), . mastermode (mastermode ), . xtal_clk (xtal_clk ), . clkout (clkout ), . gen_resetn (gen_resetn ), . risc_reset (risc_reset ), . app_clk (app_clk ), . uart_ref_clk (uart_clk_16x ) ); wire [31:0] wb_master2_rdata; wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001: (wbd_risc_adr[1:0] == 2'b01) ? 4'b0010: (wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000; assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]: (wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]: (wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]: wb_master2_rdata[31:24]; //------------------------------ // 8051 Data Memory Map // 0x0000 to 0x7FFFF - Data Memory // 0x8000 to 0x8FFF - SPI // 0x9000 to 0x9FFF - UART // 0xA000 to 0xAFFF - MAC Core //-------------------------------------------------------------- // Target ID Mapping // 4'b0100 -- MAC core // 4'b0011 -- UART // 4'b0010 -- SPI core // 4'b0001 -- External RAM // 4'b0000 -- External ROM //-------------------------------------------------------------- // wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 : (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 : (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100; wb_crossbar #(.WB_MASTER(3), .WB_SLAVE(4), .D_WD(32), .BE_WD(4), .ADR_WD(13), .TAR_WD(4)) u_wb_crossbar ( .rst_n (gen_resetn ), .clk (app_clk ), // Master Interface Signal .wbd_taddr_master ({4'b0000, wbd_tar_id, ext_reg_tid }), .wbd_din_master ({32'h0 , {wbd_risc_wdata[7:0], wbd_risc_wdata[7:0], wbd_risc_wdata[7:0], wbd_risc_wdata[7:0]}, ext_reg_wdata } ), .wbd_dout_master ({wbi_risc_rdata, wb_master2_rdata, ext_reg_rdata}), .wbd_adr_master ({wbi_risc_adr[12:0], wbd_risc_adr[14:2], ext_reg_addr[14:2]}), .wbd_be_master ({4'b1111, wb_master2_be, ext_reg_be } ), .wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ), .wbd_ack_master ({wbi_risc_ack, wbd_risc_ack, ext_reg_ack } ), .wbd_stb_master ({wbi_risc_stb, wbd_risc_stb, ext_reg_cs} ), .wbd_cyc_master ({wbi_risc_stb|wbi_risc_ack, wbd_risc_stb|wbd_risc_ack, ext_reg_cs|ext_reg_ack }), .wbd_err_master (), .wbd_rty_master (), // Slave Interface Signal .wbd_din_slave ({reg_uart_wdata, reg_spi_wdata, wb_xram_wdata, wb_xrom_wdata }), .wbd_dout_slave ({reg_uart_rdata, reg_spi_rdata, {wb_xram_rdata}, wb_xrom_rdata }), .wbd_adr_slave ({reg_uart_addr[14:2], reg_spi_addr[14:2], wb_xram_adr[14:2], wb_xrom_adr[12:0]} ), .wbd_be_slave ({reg_uart_be, reg_spi_be, wb_xram_be, wb_xrom_be} ), .wbd_we_slave ({reg_uart_wr, reg_spi_wr, wb_xram_wr, wb_xrom_wr }), .wbd_ack_slave ({reg_uart_ack, reg_spi_ack, wb_xram_ack, wb_xrom_ack }), .wbd_stb_slave ({reg_uart_cs, reg_spi_cs, wb_xram_stb, wb_xrom_stb }), .wbd_cyc_slave (), .wbd_err_slave (), .wbd_rty_slave () ); //------------------------------------- // UART core instantiation //------------------------------------- uart_core u_uart_core ( . app_reset_n (gen_resetn ), . app_clk (app_clk ), // Reg Bus Interface Signal . reg_cs (reg_uart_cs ), . reg_wr (reg_uart_wr ), . reg_addr (reg_uart_addr[5:2] ), . reg_wdata (reg_uart_wdata ), . reg_be (reg_uart_be ), // Outputs . reg_rdata (reg_uart_rdata ), . reg_ack (reg_uart_ack ), // Line Interface . si (si ), . so (so ) ); //-------------------------------- // SPI core instantiation //-------------------------------- spi_core u_spi_core ( . clk (app_clk ), . reset_n (gen_resetn ), // Reg Bus Interface Signal . reg_cs (reg_spi_cs ), . reg_wr (reg_spi_wr ), . reg_addr (reg_spi_addr[5:2] ), . reg_wdata (reg_spi_wdata ), . reg_be (reg_spi_be ), // Outputs . reg_rdata (reg_spi_rdata ), . reg_ack (reg_spi_ack ), . sck (spi_sck ), . so (spi_so ), . si (spi_si ), . cs_n (spi_cs_n ) ); oc8051_top u_8051_core ( . wb_rst_i (risc_reset ), . wb_clk_i (app_clk ), //interface to instruction rom . wbi_adr_o (wbi_risc_adr ), . wbi_dat_i (wbi_risc_rdata ), . wbi_stb_o (wbi_risc_stb ), . wbi_ack_i (wbi_risc_ack ), . wbi_cyc_o (wbi_risc_cyc ), . wbi_err_i (wbi_risc_err ), //interface to data ram . wbd_dat_i (wbd_risc_rdata ), . wbd_dat_o (wbd_risc_wdata ), . wbd_adr_o (wbd_risc_adr ), . wbd_we_o (wbd_risc_we ), . wbd_ack_i (wbd_risc_ack ), . wbd_stb_o (wbd_risc_stb ), . wbd_cyc_o (wbd_risc_cyc ), . wbd_err_i (wbd_risc_err ), // interrupt interface . int0_i ( ), . int1_i ( ), // port interface `ifdef OC8051_PORTS `ifdef OC8051_PORT0 .p0_i ( p0 ), .p0_o ( p0 ), `endif `ifdef OC8051_PORT1 .p1_i ( p1 ), .p1_o ( p1 ), `endif `ifdef OC8051_PORT2 .p2_i ( p2 ), .p2_o ( p2 ), `endif `ifdef OC8051_PORT3 .p3_i ( p3 ), .p3_o ( p3 ), `endif `endif // serial interface `ifdef OC8051_UART .rxd_i ( ), .txd_o ( ), `endif // counter interface `ifdef OC8051_TC01 .t0_i ( ), .t1_i ( ), `endif `ifdef OC8051_TC2 .t2_i ( ), .t2ex_i ( ), `endif // BIST `ifdef OC8051_BIST .scanb_rst ( ), .scanb_clk ( ), .scanb_si ( ), .scanb_so ( ), .scanb_en ( ), `endif // external access (active low) .ea_in (ea_in ) ); endmodule
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