URL
https://opencores.org/ocsvn/opb_usblite/opb_usblite/trunk
Subversion Repositories opb_usblite
[/] [opb_usblite/] [trunk/] [refdesign/] [data/] [system.ucf] - Rev 8
Compare with Previous | Blame | View Log
# Spartan-3E Starter BoardNet fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> LOC=F9 | IOSTANDARD = LVCMOS33;Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> LOC=E9 | IOSTANDARD = LVCMOS33;Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> LOC=D11 | IOSTANDARD = LVCMOS33;Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> LOC=C11 | IOSTANDARD = LVCMOS33;Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> LOC=F11 | IOSTANDARD = LVCMOS33;Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> LOC=E11 | IOSTANDARD = LVCMOS33;Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> LOC=E12 | IOSTANDARD = LVCMOS33;Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> LOC=F12 | IOSTANDARD = LVCMOS33;Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<0> LOC=N17 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<1> LOC=H18 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<2> LOC=L14 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<3> LOC=L13 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<0> LOC=D18 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<1> LOC=H13 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<2> LOC=V4 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<3> LOC=V16 | PULLDOWN | IOSTANDARD = LVCMOS33;Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=J5 | IOSTANDARD = DIFF_SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=J4 | IOSTANDARD = DIFF_SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=K3 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=K4 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=C1 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=C2 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=D1 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=K5 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=K6 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=T1 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=R3 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=R2 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=P1 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=F4 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=H4 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=H3 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=H1 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=H2 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=N4 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=T2 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=N5 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=P2 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<0> LOC=L2 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<1> LOC=L1 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<2> LOC=L3 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<3> LOC=L4 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<4> LOC=M3 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<5> LOC=M4 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<6> LOC=M5 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<7> LOC=M6 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<8> LOC=E2 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<9> LOC=E1 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<10> LOC=F1 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<11> LOC=F2 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<12> LOC=G6 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<13> LOC=G5 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<14> LOC=H6 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DQ_pin<15> LOC=H5 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=J2 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=J1 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_DQS_pin<0> LOC=L6 | IOSTANDARD = SSTL2_I;Net fpga_0_DDR_SDRAM_DDR_DQS_pin<1> LOC=G3 | IOSTANDARD = SSTL2_I | PULLUP;Net fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin LOC=P13 | IOSTANDARD = LVCMOS33;Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;Net fpga_0_clk_1_sys_clk_pin LOC=c9 | IOSTANDARD = LVCMOS33;Net fpga_0_rst_1_sys_rst_pin TIG;Net fpga_0_rst_1_sys_rst_pin LOC=K17 | IOSTANDARD = LVCMOS33 | PULLDOWN;NET opb_usblite_0_txdoe_pin LOC=B4 | IOSTANDARD = LVCMOS33;NET opb_usblite_0_rxd_pin LOC=A4 | IOSTANDARD = LVCMOS33;NET opb_usblite_0_rxdp_pin LOC=D5 | IOSTANDARD = LVCMOS33;NET opb_usblite_0_rxdn_pin LOC=C5 | IOSTANDARD = LVCMOS33;NET opb_usblite_0_txdp_pin LOC=A6 | IOSTANDARD = LVCMOS33;NET opb_usblite_0_txdn_pin LOC=B6 | IOSTANDARD = LVCMOS33;###### DDR_SDRAM############################################################################# Placement constraints for luts in tap delay ckt############################################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" RLOC=X0Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" RLOC=X0Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" RLOC=X0Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" RLOC=X0Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" RLOC=X1Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" RLOC=X1Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" RLOC=X1Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" RLOC=X1Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" RLOC=X0Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" RLOC=X0Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" RLOC=X0Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" RLOC=X0Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" RLOC=X1Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" RLOC=X1Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" RLOC=X1Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" RLOC=X1Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" RLOC=X0Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" RLOC=X0Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" RLOC=X0Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" RLOC=X0Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" RLOC=X1Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" RLOC=X1Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" RLOC=X1Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" RLOC=X1Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" RLOC=X0Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" RLOC=X0Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" RLOC=X0Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" RLOC=X0Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" RLOC=X1Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" RLOC=X1Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" RLOC=X1Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" RLOC=X1Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" U_SET = "tap_dly0_u_set";######################################################################################################################## Placement constraints for first stage flops in tap delay ckt ########################################################################################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r" RLOC=X0Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[1].r" RLOC=X0Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[1].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[2].r" RLOC=X0Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[2].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[3].r" RLOC=X0Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[3].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[4].r" RLOC=X1Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[4].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[5].r" RLOC=X1Y6;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[5].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[6].r" RLOC=X1Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[6].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[7].r" RLOC=X1Y7;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[7].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[8].r" RLOC=X0Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[8].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[9].r" RLOC=X0Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[9].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[10].r" RLOC=X0Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[10].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[11].r" RLOC=X0Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[11].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[12].r" RLOC=X1Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[12].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[13].r" RLOC=X1Y4;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[13].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[14].r" RLOC=X1Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[14].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[15].r" RLOC=X1Y5;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[15].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[16].r" RLOC=X0Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[16].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[17].r" RLOC=X0Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[17].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[18].r" RLOC=X0Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[18].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[19].r" RLOC=X0Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[19].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[20].r" RLOC=X1Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[20].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[21].r" RLOC=X1Y2;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[21].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[22].r" RLOC=X1Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[22].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[23].r" RLOC=X1Y3;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[23].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[24].r" RLOC=X0Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[24].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[25].r" RLOC=X0Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[25].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[26].r" RLOC=X0Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[26].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[27].r" RLOC=X0Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[27].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[28].r" RLOC=X1Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[28].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[29].r" RLOC=X1Y0;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[29].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[30].r" RLOC=X1Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[30].r" U_SET = "tap_dly0_u_set";INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[31].r" RLOC=X1Y1;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[31].r" U_SET = "tap_dly0_u_set";######################################################################################################################## BEL constraints for luts in tap delay ckt ########################################################################################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" BEL= F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" BEL= G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" BEL= F;############################################################################### Delay constraints#################################################################################### maxdelay of 400 ps will not be met. This constraint is just to get a better delay####NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[7]" MAXDELAY = 400ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[15]" MAXDELAY = 400ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[23]" MAXDELAY = 400ps;###### maxdelay of 460 ps will not be met. This constraint is just to get a better delay########## The reported delay will be in the range of 500 to 600 ps####NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_int_delay_in*" MAXDELAY = 480ps;###### maxdelay of 160 ps will not be met. This constraint is just to get a better delay########## The reported delay will be in the range of 200 to 360 ps####NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[*]*u_dqs_delay_col*/delay*" MAXDELAY = 200ps;#########################################################################################################constraint to place flop1 and flop2 close togather for the calibration logic ##################################################################################################################NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/flop1[*]" MAXDELAY = 3000ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/dqs_delayed_col*<*>" MAXDELAY = 1000ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/rst_dqs_div" MAXDELAY = 2500ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed*" MAXDELAY = 2000ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/fifo*_wr_en<*>" MAXDELAY = 2000ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/fifo_*_wr_addr_out<*><*>" MAXDELAY = 2000ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/fifo_*_data_out[*]" MAXDELAY = 2000ps;NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dq<*>" MAXDELAY = 480ps;######################################################################################################################## Area Group Constraint For tap_dly and cal_ctl module #########################################################################################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/cal_ctl/*" AREA_GROUP = cal_ctl;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/*" AREA_GROUP = cal_ctl;#AREA_GROUP "cal_ctl" RANGE = SLICE_X0Y10:SLICE_X15Y23; // Old valuesAREA_GROUP "cal_ctl" RANGE = SLICE_X28Y70:SLICE_X39Y83;AREA_GROUP "cal_ctl" GROUP = CLOSED;############################################################################### IOB and AREA constraints##############################################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dqs[*].dqs_iob*" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dq[*].dq_iob*" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_addr[*].addr_iob" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_ba[*].ba_iob" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_cke[*].cke_iob" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/ras_iob" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/cas_iob" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/we_iob" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_div/dqs_rst_iob" IOB = TRUE;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[1]*u_fifo_bit" LOC = SLICE_X2Y36;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X2Y37;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[0]*u_fifo_bit" LOC = SLICE_X0Y36;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X0Y37;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y32;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y33;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y32;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y33;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[5]*u_fifo_bit" LOC = SLICE_X2Y24;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X2Y25;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[4]*u_fifo_bit" LOC = SLICE_X0Y24;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X0Y25;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y20;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y21;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y20;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y21;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[1]*u_fifo_bit" LOC = SLICE_X0Y82;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X0Y83;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[0]*u_fifo_bit" LOC = SLICE_X2Y82;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X2Y83;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y76;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y77;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y76;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y77;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[5]*u_fifo_bit" LOC = SLICE_X0Y68;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X0Y69;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[4]*u_fifo_bit" LOC = SLICE_X2Y68;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X2Y69;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y64;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y65;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y64;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y65;############################################################### DQS 0 Col 0#############################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one" LOC = SLICE_X2Y29;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two" LOC = SLICE_X2Y29;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y28;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four" LOC = SLICE_X2Y28;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five" LOC = SLICE_X3Y29;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six" LOC = SLICE_X3Y28;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six" BEL = G;############################################################### DQS 0 Col 1#############################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one" LOC = SLICE_X0Y29;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two" LOC = SLICE_X0Y29;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y28;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four" LOC = SLICE_X0Y28;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five" LOC = SLICE_X1Y29;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six" LOC = SLICE_X1Y28;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six" BEL = G;############################################################### DQS 1 Col 0#############################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one" LOC = SLICE_X2Y73;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two" LOC = SLICE_X2Y73;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y72;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four" LOC = SLICE_X2Y72;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five" LOC = SLICE_X3Y73;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six" LOC = SLICE_X3Y72;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six" BEL = G;############################################################### DQS 1 Col 1#############################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one" LOC = SLICE_X0Y73;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two" LOC = SLICE_X0Y73;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y72;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four" LOC = SLICE_X0Y72;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five" LOC = SLICE_X1Y73;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six" LOC = SLICE_X1Y72;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six" BEL = G;############################################################### WR ADDR 0#############################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y30;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y30;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y31;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y31;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y30;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y30;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y31;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y31;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/*" LOC = SLICE_X1Y33;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/*" LOC = SLICE_X3Y33;############################################################### WR ADDR 1#############################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y74;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y74;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y75;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y75;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y74;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y74;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y75;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y75;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/*" LOC = SLICE_X1Y77;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/*" LOC = SLICE_X3Y77;############################################################### DQS Loopback#############################################################INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one" LOC = SLICE_X0Y9;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two" LOC = SLICE_X0Y8;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" LOC = SLICE_X0Y9;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four" LOC = SLICE_X1Y8;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four" BEL = F;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five" LOC = SLICE_X1Y8;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five" BEL = G;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six" LOC = SLICE_X1Y9;INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six" BEL = G;