Subversion Repositories openjtag-project

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 02 16:01:02 2010 " "Info: Processing started: Wed Jun 02 16:01:02 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Open_JTAG -c Open_JTAG " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Open_JTAG -c Open_JTAG" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tap_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tap_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tap_sm-rtl " "Info: Found design unit 1: tap_sm-rtl" {  } { { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 tap_sm " "Info: Found entity 1: tap_sm" {  } { { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_mux.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock_mux.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_mux-rtl " "Info: Found design unit 1: clock_mux-rtl" {  } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 clock_mux " "Info: Found entity 1: clock_mux" {  } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serializer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serializer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serializer-rtl " "Info: Found design unit 1: serializer-rtl" {  } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 serializer " "Info: Found entity 1: serializer" {  } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "open_jtag.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file open_jtag.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Open_JTAG " "Info: Found entity 1: Open_JTAG" {  } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "Open_JTAG " "Info: Elaborating entity \"Open_JTAG\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tap_sm tap_sm:inst " "Info: Elaborating entity \"tap_sm\" for hierarchy \"tap_sm:inst\"" {  } { { "Open_JTAG.bdf" "inst" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { -24 312 480 104 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_mux clock_mux:inst1 " "Info: Elaborating entity \"clock_mux\" for hierarchy \"clock_mux:inst1\"" {  } { { "Open_JTAG.bdf" "inst1" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 536 552 672 632 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serializer serializer:inst2 " "Info: Elaborating entity \"serializer\" for hierarchy \"serializer:inst2\"" {  } { { "Open_JTAG.bdf" "inst2" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 264 288 432 488 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "siwu serializer.vhd(25) " "Warning (10540): VHDL Signal Declaration warning at serializer.vhd(25): used explicit default value for signal \"siwu\" because signal was never assigned a value" {  } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 25 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst " "Warning (15610): No output dependent on input pin \"rst\"" {  } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 16 48 216 32 "rst" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "286 " "Info: Implemented 286 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Info: Implemented 257 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "187 " "Info: Peak virtual memory: 187 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 02 16:01:07 2010 " "Info: Processing ended: Wed Jun 02 16:01:07 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}