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<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Title      : PCI Parity core
</FONT></I><FONT COLOR=red><I>-- Project    : PCI target Core
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- File        : pci_parity.VHD
</FONT></I><FONT COLOR=red><I>-- Author      : Jamil Khatib  <khatib@ieee.org>
</FONT></I><FONT COLOR=red><I>-- Organization: OpenCores Project
</FONT></I><FONT COLOR=red><I>-- Created     : 2000/04/1
</FONT></I><FONT COLOR=red><I>-- Last update : 2000/04/1
</FONT></I><FONT COLOR=red><I>-- Platform    : 
</FONT></I><FONT COLOR=red><I>-- Simulators  : Modelsim 5.3XE / Windows98
</FONT></I><FONT COLOR=red><I>-- Synthesizers: webfitter - Leonardo / WindowsNT
</FONT></I><FONT COLOR=red><I>-- Target      : XC9572XL-5-VQ64 - EPF10K100EQC208 Flex10K
</FONT></I><FONT COLOR=red><I>-- Dependency  : 
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Description: PCI Parity Core
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Copyright (c) 2000 Jamil Khatib
</FONT></I><FONT COLOR=red><I>-- 
</FONT></I><FONT COLOR=red><I>-- This VHDL design file is an open design; you can redistribute it and/or
</FONT></I><FONT COLOR=red><I>-- modify it and/or implement it under the terms of the Openip General Public
</FONT></I><FONT COLOR=red><I>-- License as it is going to be published by the OpenIPCore Organization and
</FONT></I><FONT COLOR=red><I>-- any coming versions of this license.
</FONT></I><FONT COLOR=red><I>-- You can check the draft license at
</FONT></I><FONT COLOR=red><I>-- http://www.openip.org/oc/license.html
</FONT></I><FONT COLOR=red><I>--
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Revisions  :
</FONT></I><FONT COLOR=red><I>-- Revision Number : 1
</FONT></I><FONT COLOR=red><I>-- Version         :   1.0
</FONT></I><FONT COLOR=red><I>-- Date            :   1st Apr 2000
</FONT></I><FONT COLOR=red><I>-- Modifier        :   Jamil Khatib (khatib@ieee.org)
</FONT></I><FONT COLOR=red><I>-- Desccription    :   Created
</FONT></I><FONT COLOR=red><I>--
</FONT></I><FONT COLOR=red><I>-- Known bugs      : Extending the PAR signals to wait states
</FONT></I><FONT COLOR=red><I>--                 : SERR is generated upon local side request only
</FONT></I><FONT COLOR=red><I>--                 : PERR must remain active two clockcycles after the ERR
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=brown><EM>library ieee;
</FONT></EM>
<FONT COLOR=brown><EM>use ieee.std_logic_1164.all;
</FONT></EM>
 
<FONT COLOR=blue><EM>entity parity is
</FONT></EM>
 
  <FONT COLOR=yellow>port</FONT> (
    <FONT COLOR=red><I>-- PCI Interface 
</FONT></I>    CLK          : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- PCI clock
</FONT></I>    AD           : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic_vector</FONT>(31 <FONT COLOR=yellow>downto</FONT> 0);  <FONT COLOR=red><I>-- PCI AD signal
</FONT></I>    CBE          : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic_vector</FONT>(3 <FONT COLOR=yellow>downto</FONT> 0);  <FONT COLOR=red><I>-- C/BE PCI bus signals
</FONT></I>    PAR          : <FONT COLOR=yellow>inout</FONT> <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- PAR signal
</FONT></I>    SERR_n       : <FONT COLOR=yellow>inout</FONT> <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- SERR# signal
</FONT></I>    PERR_n       : <FONT COLOR=yellow>out</FONT>   <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- PERR# signal
</FONT></I>                                        <FONT COLOR=red><I>-- PERR# signal is output only for target
</FONT></I>    <FONT COLOR=red><I>-- Local Interface
</FONT></I>    ParOperation : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- Parity Operation
</FONT></I>                                        <FONT COLOR=red><I>-- Drive PAR or check it
</FONT></I>    Par_oe       : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- PAR Output Enable
</FONT></I>    Locserr_n    : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- Local System Error
</FONT></I>    LocErrRep_n  : <FONT COLOR=yellow>out</FONT>   <FONT COLOR=green>std_logic</FONT>);    <FONT COLOR=red><I>-- Local Error Report
</FONT></I>                                        <FONT COLOR=red><I>-- used to report parity errors for local interface
</FONT></I>                                        <FONT COLOR=red><I>-- and to the configuration register
</FONT></I>
<FONT COLOR=yellow>end</FONT> parity;
 
<FONT COLOR=brown><EM>library ieee;
</FONT></EM>
<FONT COLOR=brown><EM>use ieee.std_logic_1164.all;
</FONT></EM>
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=blue><EM>architecture behavior of parity is
</FONT></EM>
 
<FONT COLOR=yellow>begin</FONT>  <FONT COLOR=red><I>-- behavior
</FONT></I>
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- purpose: Parity Generation
</FONT></I><FONT COLOR=red><I>-- type   : sequential
</FONT></I><FONT COLOR=red><I>-- inputs : CLK
</FONT></I><FONT COLOR=red><I>-- outputs: PAR, LocErrRep
</FONT></I>  Paritygen : <FONT COLOR=yellow>process</FONT> (CLK)
 
    <FONT COLOR=yellow>variable</FONT> tmp_par : <FONT COLOR=green>std_logic</FONT>;       <FONT COLOR=red><I>-- temporary parity vriable
</FONT></I>    <FONT COLOR=yellow>variable</FONT> par_q   : <FONT COLOR=green>std_logic</FONT>;       <FONT COLOR=red><I>-- Next Par signal
</FONT></I>    <FONT COLOR=yellow>variable</FONT> perr_q  : <FONT COLOR=green>std_logic</FONT>;       <FONT COLOR=red><I>-- Next PERR signal
</FONT></I>
  <FONT COLOR=yellow>begin</FONT>  <FONT COLOR=red><I>-- process Paritygen
</FONT></I>
    <FONT COLOR=yellow>if</FONT> CLK'event <FONT COLOR=yellow>and</FONT> CLK = '1' <FONT COLOR=yellow>then</FONT>     <FONT COLOR=red><I>-- rising clock edge
</FONT></I>      <FONT COLOR=yellow>if</FONT> Par_oe = '1' <FONT COLOR=yellow>then</FONT>
 
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>--      PAR signal states:
</FONT></I><FONT COLOR=red><I>--      Idel: when no operation on the current target or master
</FONT></I><FONT COLOR=red><I>--          PAR = 'Z' , PERR = 'Z'
</FONT></I><FONT COLOR=red><I>--      Master Read:
</FONT></I><FONT COLOR=red><I>--        Address phase:
</FONT></I><FONT COLOR=red><I>--                 Master Drives PAR
</FONT></I><FONT COLOR=red><I>--                 Target Drives PERR
</FONT></I><FONT COLOR=red><I>--        Data phase:
</FONT></I><FONT COLOR=red><I>--                 Target Drives PAR
</FONT></I><FONT COLOR=red><I>--                 Master Drives PERR
</FONT></I><FONT COLOR=red><I>--      Master write:
</FONT></I><FONT COLOR=red><I>--        Address and data phase
</FONT></I><FONT COLOR=red><I>--                 Master Drives PAR
</FONT></I><FONT COLOR=red><I>--                 Master Drives PERR
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>--      ParOperation = 1 Calculate and drive PAR Port 
</FONT></I><FONT COLOR=red><I>--      ParOperation = 0 Calculate and report Parity Errors
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------                                       
</FONT></I>        <FONT COLOR=yellow>if</FONT> ParOperation = '1' <FONT COLOR=yellow>then</FONT>      <FONT COLOR=red><I>-- Drive PAR signal
</FONT></I>
          PAR         <= par_q;
          LocErrRep_n <= perr_q;
          PERR_n <= 'Z';
 
        <FONT COLOR=yellow>else</FONT>
 
          PERR_n <= perr_q;
          PAR <= 'Z';
 
        <FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>if</FONT>;
 
<FONT COLOR=red><I>-- No of 1's in AD, CBE & PAR must be even
</FONT></I>        tmp_par := CBE(3) <FONT COLOR=yellow>xor</FONT> CBE(2) <FONT COLOR=yellow>xor</FONT> CBE(1) <FONT COLOR=yellow>xor</FONT> CBE(0);
 
        <FONT COLOR=yellow>for</FONT> i <FONT COLOR=yellow>in</FONT> AD'<FONT COLOR=yellow>range</FONT> <FONT COLOR=yellow>loop</FONT>
 
          tmp_par := tmp_par <FONT COLOR=yellow>xor</FONT> AD(i);
 
        <FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>loop</FONT>;  <FONT COLOR=red><I>-- i
</FONT></I>
        par_q := tmp_par;
 
        perr_q := tmp_par <FONT COLOR=yellow>xor</FONT> PAR_q;
 
      <FONT COLOR=yellow>else</FONT>
 
        PAR    <= 'Z';
        PERR_n <= 'Z';
 
      <FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>if</FONT>;
    <FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>if</FONT>;
  <FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>process</FONT> Paritygen;
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I>
  SERR_n <= Locserr_n;
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=yellow>end</FONT> behavior;
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