Subversion Repositories pcie_ds_dma

[Project]
Current Flow=Multivendor
VCS=0
version=3
Current Config=compile

[Configurations]
compile=sp605_lx45t_wishbone

[Library]
sp605_lx45t_wishbone=.\sp605_lx45t_wishbone.LIB
sp605_lx45t_wishbone_post_synthesis=.\sp605_lx45t_wishbone_post_synthesis\sp605_lx45t_wishbone_post_synthesis.lib

[Settings]
AccessRead=0
AccessReadWrite=0
AccessACCB=0
AccessACCR=0
AccessReadWriteSLP=0
AccessReadTopLevel=1
DisableC=1
ENABLE_ADV_DATAFLOW=0
SYNTH_TOOL=MV_XST132
IMPL_TOOL=MV_ISE132
CSYNTH_TOOL=<none>
PHYSSYNTH_TOOL=<none>
FLOW_TYPE=HDL
LANGUAGE=VHDL
FLOWTOOLS=IMPL_WITH_SYNTH
ON_SERVERFARM_SYNTH=0
ON_SERVERFARM_IMPL=0
ON_SERVERFARM_SIM=0
DVM_DISPLAY=NO
REFRESH_FLOW=1
FAMILY=Xilinx13x SPARTAN6
RUN_MODE_SYNTH=0
VerilogDirsChanged=0
WireDelay=2
NoTchkMsg=1
NoTimingChecks=1
HESPrepare=0
EnableXtrace=0
SplitNetVectors=0
StackMemorySize=32
RetvalMemorySize=32
VsimAdditionalOptions=-relax -g test_id=2
ReportAssertionsActivations=0
TrackAssertionFailures=1
ReportAssertionsFailures=1
AssertionFailureLimit=0
AssertionFailureAction=Continue
TrackAssertionPasses=1
ReportAssertionPasses=0
AssertionPassLimit=0
ReportUnfinishedAssertions=1
TrackCoverMatches=1
ReportCoverMatches=1
CoverAction=Continue
ReportDroppedCoverEvaluations=0
ReportActivatedCoverEvaluations=0
fileopeninsrc=1
fileopenfolder=E:\prog\ds_dma_project\sp605_lx45t_wishbone
DisableVitalMsg=1
VitalAccel=1
VitalGlitches=1
DisableIEEEWarnings=1
SYNTH_STATUS=warnings
IMPL_STATUS=warnings
PHYSSYNTH_STATUS=none
PCBINTERFACE_STATUS=NONE
FUNCTIONAL_SIMULATION_STATUS=
POSTSYNTHESIS_SIMULATION_STATUS=
TIMING_SIMULATION_STATUS=
FUNC_LIB=sp605_lx45t_wishbone
POST_LIB=sp605_lx45t_wishbone_post_synthesis
RUN_MODE_IMPL=0
LAST_IMPL_STATUS=warnings
resolution=Auto

[LocalVerilogSets]
EnableSLP=1
EnableDebug=1
VerilogLanguage=4
Strict=0
Strict2001=
SystemVerilog3=
StrictLRMMode=
VerilogNoSpecify=0
WarningPrnLevel=1
ErrorOutputLimit=0
OptimizationLevel=2
ProtectLevel=0
AdditionalOptions=
MonitoringOfEventsUDP=0
DisablePulseError=0
HasInitialRegsValue=0
InitialRegsValue=X

[LocalVhdlSets]
CompileWithDebug=1
DisableVHDL87Key=0
EnableVHDL93Key=0
EnableVHDL2002Key=1
EnableVHDL2006Key=0
EnableVHDL2008Key=0
NetlistCompilation=1
Syntax RelaxLRM=0
MaxErrorsKey=100
OptimizationLevel=3
DisableRangeChecks=0
ProtectLevel=0
AdditionalOptions=
IncrementalCompilation=0
ReorderOnFirstRebuild=1
ElaborationAfterCompilation=0
PrintErrWarnOnly=0
GenMultiplatformLib=0
VhdlChangeEvalAsynchronous=0
VhdlDisableAssertionsProcessing=0

[$LibMap$]
sp605_lx45t_wishbone=.
Active_lib=SPARTAN6
xilinxun=SPARTAN6
UnlinkedDesignLibrary=SPARTAN6
DESIGNS=SPARTAN6

[IMPLEMENTATION_XILINX12]
impl_opt(dont_run_translate)=0
impl_opt(dont_run_map)=0
impl_opt(dont_run_place)=0
impl_opt(dont_run_trace)=0
impl_opt(dont_run_simulation)=0
impl_opt(dont_run_fit)=0
impl_opt(dont_run_bitgen)=1
impl_opt(use_partitions_in_flow)=0
impl_opt(partitions_file)=synthesis\xpartition.pxml

[HierarchyViewer]
SortInfo=u
HierarchyInformation=pcie_core64_m6|pcie_core64_m6|0 stend_sp605_wishbone|stend_sp605_wishbone|0 
ShowHide=ShowTopLevel
Selected=

[DefineMacro]
Global=

[Folders]
Name3=Makefiles
Directory3=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
Extension3=mak
Name4=Memory
Directory4=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\src
Extension4=mem;mif;hex
Name5=Dll Libraries
Directory5=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
Extension5=dll
Name6=PDF
Directory6=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
Extension6=pdf
Name7=HTML
Directory7=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
Extension7=

[Verilog Library]
ovi_unimacro=
ovi_unisim=
ovi_xilinxcorelib=

[SYNTHESIS]
TOPLEVEL=sp605_lx45t_wishbone
FAMILY=Xilinx13x SPARTAN6
DEVICE=6slx45tfgg484
SPEED=-3
OBSOLETE_ALIASES=1
FILTER_MESSAGES=
FSM_ENCODE=
PACK_IO_REGISTERS=Auto
SIMOUTFORM=1
AUTO_CLOSE_GUI=0
USE_DEF_UCF_FILE=1
UCF_FILENAME=
LSO_FILENAME=
HDL_INI_FILENAME=
XST_INCLUDE_PATH=src
CORES_SEARCH_DIR=
OTHER_COMMAND_LINE_OPT=
XST_WORK_DIR=synthesis\xst
PARTITIONS_FILE=
Show_OptimizationGoalCombo=Speed
Show_OptimizationEffortCombo=Normal
Show_KeepHierarchyFPGA=Yes
Show_Timing_Constraint=0
Show_FSM_Encoding_Algorithm=Auto
Show_MuxExtractionCombo=Yes
Show_Resource_Sharing=1
Show_Rom_Extraction=1
Show_Ram_Extraction=1
Show_RamStyleCombo=Auto
Show_Shift_Register_Extraction=1
Show_Add_IO_Buffer=1
Show_Equivalent_Register_Removal=0
Show_Max_Fanout=1000000
Show_Register_Duplication=0
Show_Register_Balancing=No
Show_Pack_IO_Registers_Into_IOBs=Auto
Show_Macro_Preserve=1
Show_Xor_Preserve=1
Show_WysiwygCombo=None
Show_Case_Implementation_Style=None
Show_Global_Optimalization_Goal=AllClockNets
Show_JobDescription=SynthesisTask
Show_IncludeInputFiles=*.*
Show_ExcludeInputFiles=log*.*:implement*.*
Show_UseSynthesisConstraintsFile=1
Show_CrossClockAnalysis=0
Show_HierarchySeparator=/
Show_BusDelimiter=<>
Show_GenerateRtlSchematic=Yes
Show_CaseVhdl=Maintain
Show_Verilog2001=1
Show_RomStyle=Auto
Show_ReadCores=1
Show_MaxNoBufgs16=0
Show_OptimizeInstantiatedPrimitives=0
Show_MoveFirstFlipFlopStage=<none>
Show_MoveLastFlipFlopStage=<none>
Show_FSMStyle=LUT
Show_SimulationOutputFormat=1
Show_KeepHierarchyCPLD=Yes
Show_SafeImplementation=No
Show_UseClockEnable=Auto
Show_UseSynchronousSet=Auto
Show_UseSynchronousReset=Auto
Show_FilterMessages=0
Show_DspUtilizationRatio=100
Show_LUT_FF_PairsUtilizationRatio=100
Show_PowerReduction=0
Show_BRAMUtilizationRatio=100
Show_AutomaticBRAMPacking=0
Show_AsynchronousToSynchronous=0
Show_NetlistHierarchy=As Optimized
Show_LUTCombining=Auto
Show_ReduceControlSets=Auto
Show_UseIseWithPartitions=0
Show_GenerateIseWithPartitions=1
Show_Add_Special_Library_Sources=1
Show_UseDSPBlock_S6_V6=Auto
Show_ShiftRegisterMinimumSize=2
Show_OptimizationEffortCombo_Fast=High
RAM_STYLE=Auto
ROM_STYLE=Auto
MUX_STYLE=Auto
MOVE_FIRST_FF_STAGE=1
MOVE_LAST_FF_STAGE=1
JOB_DESCRIPTION=SynthesisTask
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
JOB_SFM_RESOURCE=
LAST_RUN=1375386863
OUTPUT_NETLIST=synthesis\sp605_lx45t_wishbone.ngc
OUTPUT_SIMUL_NETLIST=synthesis\sp605_lx45t_wishbone.vhd

[PHYS_SYNTHESIS]
FAMILY=Xilinx13x SPARTAN6
DEVICE=6slx45tfgg484
SPEED=-3
SCRIPTS_COPIED=0
IN_DESIGN=synthesis\sp605_lx45t_wishbone.ngc
OUT_DESIGN=
IN_CONSTRAINT=
OUT_CONSTRAINT=
REPORT=

[IMPLEMENTATION]
FLOW_STEPS_RESET=0
FAMILY=Xilinx13x SPARTAN6
DEVICE=6slx45tfgg484
SPEED=-3
NETLIST=synthesis\sp605_lx45t_wishbone.ngc
IS_BAT_MODE=0
BAT_FILE=
UCF=src\top\sp605_lx45t_wishbone.ucf
DEF_UCF=2
OLD_FAMILY=Xilinx13x SPARTAN6
wasChanged_Change_Device_Speed=0
wasChanged_Change_Device_Speed_To=0
wasChanged_Change_Device_Speed_To2=1
Place_And_Route_Mode_old_value=Route Only
JOB_DESCRIPTION=ImplementationTask
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
JOB_SFM_RESOURCE=
SYNTH_TOOL_RESET=0
LAST_RUN=1375387391

[IMPLEMENTATION_XILINX13]
impl_opt(dont_run_translate)=0
impl_opt(dont_run_map)=0
impl_opt(dont_run_place)=0
impl_opt(dont_run_trace)=0
impl_opt(dont_run_simulation)=1
impl_opt(dont_run_fit)=0
impl_opt(dont_run_bitgen)=0
Macro_Search_Path={src\wishbone\coregen} {src\pcie_src\components\coregen}
impl_opt(partitions_file)=
impl_opt(use_partitions_file)=0
impl_opt(smart_guide_file)=implement\ver1\rev1\sp605_lx45t_wishbone_guide.ncd
impl_opt(use_smart_guide)=0
impl_opt(edif_str)=synthesis\sp605_lx45t_wishbone.ngc
impl_opt(_family_sel)=Xilinx13x SPARTAN6
impl_opt(_device_sel)=6slx45tfgg484
impl_opt(_speed_sel)=-3
impl_opt(Effort_Level)=High
impl_opt(netlist_format)=1
impl_opt(auto_close)=0
impl_opt(override_existing_project)=1
impl_opt(bat_file_name)=
impl_opt(is_bat_mode)=0
impl_opt(def_ucf)=Custom constraint file
impl_opt(ucf_str)=src\top\sp605_lx45t_wishbone.ucf
impl_opt(version_sel)=ver1
impl_opt(revision_sel)=rev1
impl_opt(insert_pads)=0
impl_opt(Pack_IO_Registers_Latches)=For Inputs and Outputs
impl_opt(ignore_rloc_constraints)=1
impl_opt(create_detailed_report)=0
impl_opt(ngdbuild_file_str)=
impl_opt(use_ngdbuild_file)=0
impl_opt(map_file_str)=
impl_opt(use_map_file)=0
impl_opt(par_file_str)=
impl_opt(use_par_file)=0
impl_opt(trace_file_str)=
impl_opt(use_trace_file)=0
impl_opt(netgen_file_str)=
impl_opt(use_netgen_file)=0
impl_opt(bitgen_file_str)=
impl_opt(use_bitgen_file)=0
impl_opt(Allow_Unmatched_LOC_Constraint)=1
impl_opt(Show_Trim_Unconnected_Signals)=1
impl_opt(Place_And_Route_Mode)=Route Only
impl_opt(Show_Generate_Multiple_Hierarchical_Netlist_Files)=0
impl_opt(Show_Bring_Out_Global_Trisate_Net_As_Ports)=
impl_opt(Use_Show_Bring_Out_Global_Trisate_Net_As_Ports)=0
impl_opt(Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=
impl_opt(Use_Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=0
impl_opt(Show_Generate_Testbench_File)=UUT
impl_opt(Use_Show_Generate_Testbench_File)=0
impl_opt(Netlist_Translation_Type)=Timestamp
impl_opt(Allow_Unexpanded_Blocks)=0
impl_opt(Other_Ngdbuild_Options)=
impl_opt(Map_Effort_Level)=High
impl_opt(Allow_Logic_Opt_Across_Hier)=1
impl_opt(Use_Rloc_Constraints)=Yes
impl_opt(Show_Map_Slice_Logic_Into_Unused_Blocks)=0
impl_opt(Other_Map_Options)=
impl_opt(Extra_Effort)=Normal
impl_opt(Retain_Hiearchy)=1
impl_opt(Change_Device_Speed)=3
impl_opt(Tristate_Configuration_Pulsee)=0
impl_opt(Reset_Configuration_Pulsee)=100
impl_opt(Generate_Architecture_Only)=0
impl_opt(Include_Uselib_Directive)=0
impl_opt(Do_Not_Escape_Signal)=0
impl_opt(Other_Netgen_Command)=
impl_opt(Show_Other_Place_Route_Command)=
impl_opt(Use_Rules_File_For_Nelist)=
impl_opt(Path_Used_In_Sdf)=implement
impl_opt(Insert_ChipScope_Core)=0
impl_opt(Run_ChipScope_Core_Inserter_GUI)=1
impl_opt(ChipScope_Core_Inserter_Project_File)=synthesis\sp605_lx45t_wishbone.cdc
impl_opt(_use_filter_messages)=0
impl_opt(_filter_messages)=
impl_opt(AdvMap_Extra_Effort)=Normal
impl_opt(Map_Starting_Placer_Cost_Table)=1
impl_opt(Show_Register_Duplication)=0
impl_opt(Include_Function_In_Verilog_File)=1
impl_opt(Include_Simprim_Models_In_Verilog_File)=0
impl_opt(Show_Equivalent_Register_Removal)=1
impl_opt(run_design_rules_checker)=1
impl_opt(create_bit_file)=1
impl_opt(create_binary_config_file)=0
impl_opt(create_ascii_config_file)=0
impl_opt(create_ieee_1532_config_file_fpga)=0
impl_opt(enable_bitstream_compression)=1
impl_opt(enable_debugging_of_serial_mode_bitstream)=0
impl_opt(enable_cyclic_redundancy_checking)=1
impl_opt(other_bitgen_command_line_options)=
impl_opt(security)=Enable Readback and Reconfiguration
impl_opt(create_readback_data_files)=0
impl_opt(allow_selectmap_pins_to_persist)=0
impl_opt(create_logic_allocation_file)=0
impl_opt(create_mask_file)=0
impl_opt(encrypt_bitstream)=0
impl_opt(key_0)=
impl_opt(input_encryption_key_file)=
impl_opt(starting_cbc_value)=
impl_opt(fpga_start_up_clock)=CCLK
impl_opt(enable_internal_done_pipe)=0
impl_opt(done_output_events)=4
impl_opt(enable_outputs)=5
impl_opt(release_write_enable)=6
impl_opt(drive_done_pin_high)=1
impl_opt(configuration_rate)=2
impl_opt(configuration_pin_program)=Pull Up
impl_opt(configuration_pin_done)=Pull Up
impl_opt(jtag_pin_tck)=Pull Up
impl_opt(jtag_pin_tdi)=Pull Up
impl_opt(jtag_pin_tdo)=Pull Up
impl_opt(jtag_pin_tms)=Pull Up
impl_opt(unused_iob_pins)=Pull Up
impl_opt(userid_code)=0xFFFFFFFF
impl_opt(merge_netlists_before_insertion)=1
impl_opt(chipscope_bat_file_str)=
impl_opt(use_chipscope_bat_file)=0
impl_opt(Rename_Top_Level_Architecture_to)=Structure
impl_opt(Rename_Top_Level_Entity_to)=
impl_opt(Rename_Top_Level_Module_to)=
impl_opt(Combinatorial_Logic_Optimization)=1
impl_opt(Generate_Asynchronous_Delay_Report)=0
impl_opt(Generate_Clock_Region_Report)=0
impl_opt(Power_Reduction_Par)=0
impl_opt(Enable_Incremental_Design_Flow)=0
impl_opt(Run_Guided_Incremental_Design_Flow)=0
impl_opt(Report_Type)=Verbose report
impl_opt(Number_of_items_in_Error_Verbose_Report)=3
impl_opt(Perform_Advanced_Analysis)=0
impl_opt(Change_Device_Speed_To)=3
impl_opt(Report_Uncovered_Paths)=
impl_opt(Report_Fastest_Path_in_Each_Constraint)=1
impl_opt(post_map_file_str)=
impl_opt(use_post_map_file)=0
impl_opt(Report_Type2)=Error report
impl_opt(Number_of_items_in_Error_Verbose_Report2)=3
impl_opt(Perform_Advanced_Analysis2)=0
impl_opt(Change_Device_Speed_To2)=3
impl_opt(Report_Uncovered_Paths2)=
impl_opt(Report_Fastest_Path_in_Each_Constraint2)=1
impl_opt(Stamp_Timing_Model_Filename)=
impl_opt(Constraints_Interaction_Report_File2)=
impl_opt(dont_run_post_map_trace)=1
impl_opt(automatically_insert_glbl_module)=1
impl_opt(maximum_compression)=0
impl_opt(Output_Extended_Identifiers)=0
impl_opt(enable_suspend_wake_global_set_reset)=0
impl_opt(drive_awake_pin_during_suspend_wake_sequence)=0
impl_opt(wakeup_control)=Startup Clock
impl_opt(gwe_cycle_during_suspend_wakeup_sequence)=5
impl_opt(gts_cycle_during_suspend_wakeup_sequence)=4
impl_opt(ChipScope_Overwrite_Project_File)=0
impl_opt(insert_buffers_to_prevent_pulse_swallowing)=1
impl_opt(Report_Paths_By_Endpoint)=3
impl_opt(Generate_Datasheet_Section)=1
impl_opt(Generate_Timegroups_Section)=0
impl_opt(Constraints_Interaction_Report_File)=
impl_opt(Ignore_User_Timing_Constraints_Map)=0
impl_opt(Power_Activity_File_Map)=
impl_opt(Ignore_User_Timing_Constraints_Par)=0
impl_opt(Timing_Mode_Par)=Performance Evaluation
impl_opt(Power_Activity_File_Par)=
impl_opt(Report_Paths_By_Endpoint2)=3
impl_opt(Generate_Datasheet_Section2)=1
impl_opt(Generate_Timegroups_Section2)=0
impl_opt(retry_configuration_if_crc_error_occurs)=0
impl_opt(place_multiboot_settings_into_bitstream)=0
impl_opt(multiboot_starting_address_for_next_configuration)=0x00000000
impl_opt(multiboot_use_new_mode_for_next_configuration)=1
impl_opt(multiboot_next_configuration_mode)=001
impl_opt(Timing_Mode_Map_Virtex5)=Performance Evaluation
impl_opt(LUT_Combining)=Auto
impl_opt(Global_Optimization_Virtex5)=Off
impl_opt(Enable_Multi_Threading_Map)=Off
impl_opt(enable_external_master_clock)=0
impl_opt(setup_external_master_clock_division)=1
impl_opt(set_spi_configuration_bus_width)=1
impl_opt(multiboot_starting_address_for_golden_configuration)=0x00000000
impl_opt(multiboot_user_defined_register_for_failsafe_scheme)=0x0000
impl_opt(wait_for_dcm_and_pll_lock)=NoWait
impl_opt(enable_multi_pin_wake_up_suspend_mode)=0
impl_opt(mask_pins_for_multi_pin_wake_up_suspend_mode)=0x00
impl_opt(encrypt_key_select)=BBRAM
impl_opt(Watchdog_Timer_Value_Spartan6)=0xFFFF
impl_opt(Allow_Unmatched_Timing_Group_Constraints)=0
impl_opt(Extra_Cost_Tables)=0
impl_opt(Enable_Multi_Threading_Par)=Off
impl_opt(Power_Reduction_Map_Virtex6)=Off
impl_opt(Register_Ordering)=4

[PCB_INTERFACE]
FAMILY=

[Groups]
pcie_src=1
pcie_src\components=1
pcie_src\components\block_main=1
pcie_src\components\pcie_core=1
pcie_src\components\rtl=1
pcie_src\pcie_core64_m1=1
pcie_src\pcie_core64_m1\pcie_ctrl=1
pcie_src\pcie_core64_m1\pcie_fifo_ext=1
pcie_src\pcie_core64_m1\source=0
pcie_src\pcie_core64_m1\source_s6=1
pcie_src\pcie_core64_m1\source_virtex6=1
pcie_src\pcie_core64_m1\top=1
pcie_src\pcie_sim=1
pcie_src\pcie_sim\dsport=1
pcie_src\pcie_sim\sim=1
testbench=1
testbench\modelsim=1
testbench\modelsim\zz_do=1
testbench\modelsim\required_tests=1
testbench\modelsim\required_tests\test0=1
testbench\modelsim\required_tests\test0\zz_do=1
testbench\ahdl=1
testbench\log=1
top=1
wishbone=1
wishbone\block_test_check=1
wishbone\block_test_generate=1
wishbone\cross=1
wishbone\doc=1
wishbone\coregen=1
wishbone\testbecnh=0
wishbone\testbecnh\dev_pb_wishbone_ctrl=1
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim=1
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do=1
wishbone\testbecnh\dev_test_check=1
wishbone\testbecnh\dev_test_check\sim=1
wishbone\testbecnh\dev_test_check\sim\zz_do=1
wishbone\testbecnh\dev_test_gen=1
wishbone\testbecnh\dev_test_gen\sim=1
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
wishbone\testbecnh\dev_wb_cross=1
wishbone\testbecnh\dev_wb_cross\sim=1
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
post-synthesis=0
DESIGN_STATUS=1
DESIGN_STATUS\2013_07_26_01_18=1
DESIGN_STATUS\2013_08_02_00_11=1
wishbone\doc\en=1
wishbone\doc\ru=1
pcie_src\components\coregen_s6=1

[Files]
pcie_src\components\block_main/block_pe_main.vhd=-1
pcie_src\components\pcie_core/pcie_core64_m2.vhd=-1
pcie_src\components\pcie_core/pcie_core64_m5.vhd=-1
pcie_src\components\pcie_core/pcie_core64_m7.vhd=-1
pcie_src\components\pcie_core/pcie_core64_wishbone.vhd=-1
pcie_src\components\pcie_core/pcie_core64_wishbone_m8.vhd=-1
pcie_src\components\rtl/host_pkg.vhd=-1
pcie_src\components\rtl/core64_pb_transaction.vhd=-1
pcie_src\components\rtl/ctrl_ram16_v1.vhd=-1
pcie_src\components\rtl/core64_pb_wishbone.vhd=-1
pcie_src\components\rtl/core64_pb_wishbone_ctrl.v=-1
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.ngc=-1
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.vhd=-1
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.xco=-1
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.ngc=-1
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.vhd=-1
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.xco=-1
pcie_src\components\coregen_s6/ctrl_fifo64x37st.ngc=-1
pcie_src\components\coregen_s6/ctrl_fifo64x37st.vhd=-1
pcie_src\components\coregen_s6/ctrl_fifo64x37st.xco=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_type_pkg.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_interrupt.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_pb_disp.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_reg_access.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m2.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m4.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m2.vhd=-1
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m4.vhd=-1
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_adr.vhd=-1
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_ext_cmd.vhd=-1
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_descriptor.vhd=-1
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_main.vhd=-1
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd_pb.vhd=-1
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd.vhd=-1
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_ram.vhd=-1
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[Files.Data]
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