Subversion Repositories pcie_sg_dma

##-----------------------------------------------------------------------------
##
## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information of Xilinx, Inc.
## and is protected under U.S. and international copyright and other
## intellectual property laws.
##
## DISCLAIMER
##
## This disclaimer is not a license and does not grant any rights to the
## materials distributed herewith. Except as otherwise provided in a valid
## license issued to you by Xilinx, and to the maximum extent permitted by
## applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
## FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
## IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
## MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
## and (2) Xilinx shall not be liable (whether in contract or tort, including
## negligence, or under any other theory of liability) for any loss or damage
## of any kind or nature related to, arising under or in connection with these
## materials, including for any direct, or any indirect, special, incidental,
## or consequential loss or damage (including loss of data, profits, goodwill,
## or any type of loss or damage suffered as a result of any action brought by
## a third party) even if such damage or loss was reasonably foreseeable or
## Xilinx had been advised of the possibility of the same.
##
## CRITICAL APPLICATIONS
##
## Xilinx products are not designed or intended to be fail-safe, or for use in
## any application requiring fail-safe performance, such as life-support or
## safety devices or systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any other
## applications that could lead to death, personal injury, or severe property
## or environmental damage (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and liability of any use of
## Xilinx products in Critical Applications, subject only to applicable laws
## and regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
## AT ALL TIMES.
##
##-----------------------------------------------------------------------------
## Project    : Virtex-6 Integrated Block for PCI Express
## File       : xilinx_pcie_2_0_ep_v6_04_lane_gen1_xc6vlx240t-ff1156-1_ML605.ucf
#
###############################################################################
# Define Device, Package And Speed Grade
###############################################################################

CONFIG PART = xc6vlx240t-ff1156-1;


###############################################################################
# Pinout and Related I/O Constraints
###############################################################################

#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#

NET "sys_reset_n" TIG;
NET "sys_reset_n" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

#
#
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-6 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-6 GT Transceiver User Guide 
# (UG) for guidelines regarding clock resource selection.
#

#NET "sys_clk_n" LOC = P6;
#NET "sys_clk_p" LOC = P5;
INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6;

#
# Transceiver instance placement.  This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Virtex-6 GT Transceiver User Guide (UG) for more information.
#


INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;

## PCIe Lane 0
#INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;
## PCIe Lane 1
#INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX" LOC = GTXE1_X0Y14;
## PCIe Lane 2
#INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX" LOC = GTXE1_X0Y13;
## PCIe Lane 3
#INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX" LOC = GTXE1_X0Y12;

#
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used.
#

INST "make4Lanes.pcieCore/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;

# SIMONE aggiunti da v1.3 to v1.6
INST "make4Lanes.pcieCore/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;
# SIMONE aggiunti da v1.3 to v1.6



###############################################################################
# Timing Constraints
###############################################################################

#
# Timing requirements and related constraints.
#

NET "sys_clk_c" TNM_NET = "SYSCLK" ;
NET "make4Lanes.pcieCore/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ;

TIMESPEC "TS_SYSCLK"  = PERIOD "SYSCLK" 100 MHz HIGH 50 % PRIORITY 100 ;
TIMESPEC "TS_CLK_125"  = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 1 ;


PIN "make4Lanes.pcieCore/trn_reset_n_int_i.CLR" TIG ;
PIN "make4Lanes.pcieCore/trn_reset_n_i.CLR" TIG ;
PIN "make4Lanes.pcieCore/pcie_clocking_i/mmcm_adv_i.RST" TIG ;


#For PCIe gen2 x1 !!!
NET "make4Lanes.pcieCore/pcie_clocking_i/clk_250" TNM_NET = "CLK_250" ;
TIMESPEC "TS_CLK_250" = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 1;
NET "make4Lanes.pcieCore/pcie_clocking_i/sel_lnk_rate_d" TIG ;



###############################################################################
# Physical Constraints
###############################################################################

INST "make4Lanes.pcieCore/*" AREA_GROUP = "AG_core" ;
AREA_GROUP "AG_core" RANGE = SLICE_X136Y147:SLICE_X155Y120 ;

###############################################################################
# End
###############################################################################




#### Module LEDs_8Bit constraints

Net LEDs_IO_pin<0> LOC = AC22;   
Net LEDs_IO_pin<1> LOC = AC24;  
Net LEDs_IO_pin<2> LOC = AE22;  
Net LEDs_IO_pin<3> LOC = AE23;  

Net LEDs_IO_pin<4> LOC = AB23;
Net LEDs_IO_pin<5> LOC = AG23;
Net LEDs_IO_pin<6> LOC = AE24;
Net LEDs_IO_pin<7> LOC = AD24;
Net LEDs_IO_pin<*> IOSTANDARD=LVCMOS25;


NET "userclk_66MHz" PERIOD = 66.6 MHz HIGH 50%;
NET "userclk_66MHz" LOC = "U23";

NET "userclk_200MHz_n" LOC = "H9";
NET "userclk_200MHz_p" LOC = "J9";
NET "userclk_200MHz_p" PERIOD = 200 MHz HIGH 50%;



#### Module DIP_Switches constraints
#Net dummy_pin_in<0> LOC=D22;
#Net dummy_pin_in<1> LOC=C22;
#Net dummy_pin_in<2> LOC=L21;
##Net SWITCH_pin<3> LOC=L20;
##Net SWITCH_pin<4> LOC=C18;
##Net SWITCH_pin<5> LOC=B18;
##Net SWITCH_pin<6> LOC=K22;
##Net SWITCH_pin<7> LOC=K21;
#Net dummy_pin_in<*> IOSTANDARD = SSTL15;