Subversion Repositories pcie_sg_dma

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/Temp/Xilinx PCI

   Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/PCIe_UserLogic_00.vhd" into

   library work

INFO:ProjectMgmt - Parsing design hierarchy completed successfully.

INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.

   Please set the new top explicitly by running the "project set top" command.

   To re-calculate the new top automatically, set the "Auto Implementation Top"

   property to true.