OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [globals] - Rev 13

Compare with Previous | Blame | View Log

{
  'XILINX' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
  'clkWrapper' => 'inout_logic_cw',
  'clkWrapperFile' => 'inout_logic_cw.vhd',
  'createTestbench' => 0,
  'design' => 'inout_logic',
  'designFileList' => [
    'inout_logic.vhd',
    'inout_logic_cw.vhd',
  ],
  'device' => 'xc6vlx240t-1ff1156',
  'family' => 'virtex6',
  'files' => [
    'xlpersistentdff.ngc',
    'synopsis',
    'inout_logic.vhd',
    'xlpersistentdff.ngc',
    'inout_logic_cw.vhd',
    'inout_logic_cw.ucf',
    'inout_logic_cw.xcf',
    'inout_logic_cw.sdc',
    'xst_inout_logic.prj',
    'xst_inout_logic.scr',
    'vcom.do',
    'isim_inout_logic.prj',
  ],
  'hdlKind' => 'vhdl',
  'isCombinatorial' => 1,
  'synthesisTool' => 'XST',
  'sysgen' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
  'systemClockPeriod' => 5,
  'testbench' => 0,
  'using71Netlister' => 1,
  'vsimtime' => '6875000275.000000 ns',
}

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.