Subversion Repositories pcie_sg_dma

{
  'attributes' => {
    'HDLCodeGenStatus' => 0,
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
    'Impl_file' => 'ISE Defaults',
    'Impl_file_sgadvanced' => '',
    'Synth_file' => 'XST Defaults',
    'Synth_file_sgadvanced' => '',
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
    'base_system_period_hardware' => 5,
    'base_system_period_simulink' => '5e-009',
    'block_icon_display' => 'Default',
    'block_type' => 'sysgen',
    'block_version' => '',
    'ce_clr' => 0,
    'clkWrapper' => 'user_logic_cw',
    'clkWrapperFile' => 'user_logic_cw.vhd',
    'clock_loc' => '',
    'clock_wrapper' => 'Clock Enables',
    'clock_wrapper_sgadvanced' => '',
    'compilation' => 'NGC Netlist',
    'compilation_lut' => {
      'keys' => [
        'HDL Netlist',
        'Bitstream',
        'NGC Netlist',
      ],
      'values' => [
        'target1',
        'target2',
        'target3',
      ],
    },
    'compilation_target' => 'NGC Netlist',
    'core_generation' => 1,
    'core_generation_sgadvanced' => '',
    'core_is_deployed' => 0,
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c1fefddc63a4b8747',
    'coregen_part_family' => 'virtex6',
    'createTestbench' => 0,
    'create_interface_document' => 'off',
    'dbl_ovrd' => -1,
    'dbl_ovrd_sgadvanced' => '',
    'dcm_info' => {
    },
    'dcm_input_clock_period' => 5,
    'deprecated_control' => 'off',
    'deprecated_control_sgadvanced' => '',
    'design' => 'user_logic',
    'designFile' => 'user_logic.vhd',
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\ML605_ISE13.3\\MySysGen\\PCIe_UserLogic_00.mdl',
    'device' => 'xc6vlx240t-1ff1156',
    'device_speed' => -1,
    'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
    'entityNamingInstrs' => {
      'nameMap' => undef,
      'namesAlreadyUsed' => {
        'default_clock_driver' => 1,
        'user_logic_cw' => 1,
      },
    },
    'eval_field' => 0,
    'fileAttributes' => {
      'cntr_11_0_341fbb8cfa0e669e.ngc' => {
        'producer' => 'coregen',
      },
      'icon_1_06_a_87e2f476e984e565.ngc' => {
        'producer' => 'coregen',
      },
      'ila_1_05_a_b6735eb4b876dee5.ngc' => {
        'producer' => 'coregen',
      },
    },
    'files' => [
      'cntr_11_0_341fbb8cfa0e669e.ngc',
      'icon_1_06_a_87e2f476e984e565.ngc',
      'ila_1_05_a_b6735eb4b876dee5.ngc',
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      'synopsis',
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      'xlpersistentdff.ngc',
      'user_logic_cw.vhd',
      'user_logic_cw.ucf',
      'user_logic_cw.xcf',
      'user_logic_cw.sdc',
      'xst_user_logic.prj',
      'xst_user_logic.scr',
      'vcom.do',
      'isim_user_logic.prj',
      'globals',
      'hdlFiles',
      'user_logic_cw.xise',
      'user_logic_cw.gise',
      'user_logic_cw.sgp',
    ],
    'fxdptinstalled' => 1,
    'generateUsing71FrontEnd' => 1,
    'generating_island_subsystem_handle' => 2341.00048828125,
    'generating_subsystem_handle' => 2341.00048828125,
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
    'has_advanced_control' => 0,
    'hdlDir' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl',
    'hdlKind' => 'vhdl',
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
    'impl_file' => 'ISE Defaults*',
    'incr_netlist' => 'off',
    'incr_netlist_sgadvanced' => '',
    'infoedit' => ' System Generator',
    'isdeployed' => 0,
    'ise_version' => '13.3i',
    'master_sysgen_token_handle' => 2342.00048828125,
    'matlab' => 'C:/Programmi/MATLAB/R2010b',
    'matlab_fixedpoint' => 1,
    'mdlHandle' => 2083.00048828125,
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
    'modelDiagnostics' => [
      {
        'count' => 351,
        'isMask' => 0,
        'type' => 'PCIe_UserLogic_00 Total blocks',
      },
      {
        'count' => 4,
        'isMask' => 0,
        'type' => 'DiscretePulseGenerator',
      },
      {
        'count' => 339,
        'isMask' => 0,
        'type' => 'S-Function',
      },
      {
        'count' => 4,
        'isMask' => 0,
        'type' => 'SubSystem',
      },
      {
        'count' => 4,
        'isMask' => 0,
        'type' => 'Terminator',
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        'type' => 'Xilinx Counter Block',
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        'count' => 44,
        'isMask' => 1,
        'type' => 'Xilinx Gateway In Block',
      },
      {
        'count' => 39,
        'isMask' => 1,
        'type' => 'Xilinx Gateway Out Block',
      },
      {
        'count' => 2,
        'isMask' => 1,
        'type' => 'Xilinx Inverter Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx Logical Block Block',
      },
      {
        'count' => 89,
        'isMask' => 1,
        'type' => 'Xilinx Register Block',
      },
      {
        'count' => 62,
        'isMask' => 1,
        'type' => 'Xilinx Shared Memory Based From Register Block',
      },
      {
        'count' => 62,
        'isMask' => 1,
        'type' => 'Xilinx Shared Memory Based To Register Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx Subsystem Generator Block',
      },
      {
        'count' => 2,
        'isMask' => 1,
        'type' => 'Xilinx System Generator Block',
      },
      {
        'count' => 14,
        'isMask' => 1,
        'type' => 'Xilinx Type Converter Block',
      },
    ],
    'model_globals_initialized' => 1,
    'model_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
    'myxilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
    'ngc_config' => {
      'include_cf' => 1,
      'include_clockwrapper' => 1,
    },
    'ngc_files' => [
      'xlpersistentdff.ngc',
    ],
    'num_sim_cycles' => 2000000000,
    'package' => 'ff1156',
    'part' => 'xc6vlx240t',
    'partFamily' => 'virtex6',
    'port_data_types_enabled' => 1,
    'postgeneration_fcn' => 'xlNGCPostGeneration',
    'preserve_hierarchy' => 0,
    'proj_type' => 'Project Navigator',
    'proj_type_sgadvanced' => '',
    'run_coregen' => 'off',
    'run_coregen_sgadvanced' => '',
    'sample_time_colors_enabled' => 1,
    'sampletimecolors' => 1,
    'sdcFile' => 'user_logic_cw.sdc',
    'settings_fcn' => 'xlngcsettings',
    'sg_blockgui_xml' => '',
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
    'sg_list_contents' => '',
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');',
    'sg_version' => '',
    'sggui_pos' => '-1,-1,-1,-1',
    'simulation_island_subsystem_handle' => 2341.00048828125,
    'simulinkName' => 'parking_lot',
    'simulink_accelerator_running' => 0,
    'simulink_debugger_running' => 0,
    'simulink_period' => '5e-009',
    'speed' => -1,
    'synth_file' => 'XST Defaults*',
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    'synthesis_tool' => 'XST',
    'synthesis_tool_sgadvanced' => '',
    'sysclk_period' => 5,
    'sysgen' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
    'sysgenRoot' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
    'sysgenTokenSettings' => {
      'Impl_file' => 'ISE Defaults',
      'Impl_file_sgadvanced' => '',
      'Synth_file' => 'XST Defaults',
      'Synth_file_sgadvanced' => '',
      'base_system_period_hardware' => 5,
      'base_system_period_simulink' => '5e-009',
      'block_icon_display' => 'Default',
      'block_type' => 'sysgen',
      'block_version' => '',
      'ce_clr' => 0,
      'clock_loc' => '',
      'clock_wrapper' => 'Clock Enables',
      'clock_wrapper_sgadvanced' => '',
      'compilation' => 'NGC Netlist',
      'compilation_lut' => {
        'keys' => [
          'HDL Netlist',
          'Bitstream',
          'NGC Netlist',
        ],
        'values' => [
          'target1',
          'target2',
          'target3',
        ],
      },
      'core_generation' => 1,
      'core_generation_sgadvanced' => '',
      'coregen_part_family' => 'virtex6',
      'create_interface_document' => 'off',
      'dbl_ovrd' => -1,
      'dbl_ovrd_sgadvanced' => '',
      'dcm_input_clock_period' => 5,
      'deprecated_control' => 'off',
      'deprecated_control_sgadvanced' => '',
      'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
      'eval_field' => 0,
      'has_advanced_control' => 0,
      'impl_file' => 'ISE Defaults*',
      'incr_netlist' => 'off',
      'incr_netlist_sgadvanced' => '',
      'infoedit' => ' System Generator',
      'master_sysgen_token_handle' => 2342.00048828125,
      'ngc_config' => {
        'include_cf' => 1,
        'include_clockwrapper' => 1,
      },
      'package' => 'ff1156',
      'part' => 'xc6vlx240t',
      'postgeneration_fcn' => 'xlNGCPostGeneration',
      'preserve_hierarchy' => 0,
      'proj_type' => 'Project Navigator',
      'proj_type_sgadvanced' => '',
      'run_coregen' => 'off',
      'run_coregen_sgadvanced' => '',
      'settings_fcn' => 'xlngcsettings',
      'sg_blockgui_xml' => '',
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
      'sg_list_contents' => '',
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');',
      'sggui_pos' => '-1,-1,-1,-1',
      'simulation_island_subsystem_handle' => 2341.00048828125,
      'simulink_period' => '5e-009',
      'speed' => -1,
      'synth_file' => 'XST Defaults*',
      'synthesis_language' => 'vhdl',
      'synthesis_tool' => 'XST',
      'synthesis_tool_sgadvanced' => '',
      'sysclk_period' => 5,
      'testbench' => 0,
      'testbench_sgadvanced' => '',
      'trim_vbits' => 1,
      'trim_vbits_sgadvanced' => '',
      'xilinx_device' => 'xc6vlx240t-1ff1156',
      'xilinxfamily' => 'virtex6',
    },
    'sysgen_Root' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
    'systemClockPeriod' => 5,
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
    'testbench' => 0,
    'testbench_sgadvanced' => '',
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen',
    'trim_vbits' => 1,
    'trim_vbits_sgadvanced' => '',
    'ucfFile' => 'user_logic_cw.ucf',
    'use_ce_syn_keep' => 1,
    'use_strict_names' => 1,
    'user_tips_enabled' => 0,
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
    'using71Netlister' => 1,
    'verilog_files' => [
      'conv_pkg.v',
      'synth_reg.v',
      'synth_reg_w_init.v',
      'convert_type.v',
    ],
    'version' => '',
    'vhdl_files' => [
      'conv_pkg.vhd',
      'synth_reg.vhd',
      'synth_reg_w_init.vhd',
    ],
    'vsimtime' => '11000000275.000000 ns',
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    'xilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
    'xilinx_device' => 'xc6vlx240t-1ff1156',
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    'xilinx_package' => 'ff1156',
    'xilinx_part' => 'xc6vlx240t',
    'xilinxdevice' => 'xc6vlx240t-1ff1156',
    'xilinxfamily' => 'virtex6',
    'xilinxpart' => 'xc6vlx240t',
  },
  'entityName' => '',
  'nets' => {
    '.bram_rd_dout' => {
      'hdlType' => 'std_logic_vector(63 downto 0)',
      'width' => 64,
    },
    '.clk' => {
      'hdlType' => 'std_logic',
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    },
    '.fifo_rd_count' => {
      'hdlType' => 'std_logic_vector(14 downto 0)',
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    },
    '.fifo_rd_dout' => {
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      'width' => 72,
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    '.fifo_rd_empty' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    '.fifo_rd_pempty' => {
      'hdlType' => 'std_logic',
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    },
    '.fifo_rd_valid' => {
      'hdlType' => 'std_logic',
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    },
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      'hdlType' => 'std_logic_vector(14 downto 0)',
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    },
    '.fifo_wr_full' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    '.fifo_wr_pfull' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    '.rst_i' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'from_register.data_out' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
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      'hdlType' => 'std_logic',
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      'width' => 32,
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      'width' => 12,
    },
    'sysgen_dut.bram_wr_addr' => {
      'hdlType' => 'std_logic_vector(11 downto 0)',
      'width' => 12,
    },
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    },
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    },
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    },
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      'hdlType' => 'std_logic',
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    },
    'sysgen_dut.rst_o' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register10_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register10_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register10_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register10_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register10_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register11_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register11_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register11_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register11_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register11_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register12_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register12_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register12_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register12_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register12_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register13_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register13_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register13_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register13_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register13_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register14_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register14_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register14_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register14_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register14_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register15_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register15_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register15_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register15_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register15_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register16_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register16_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register16_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register16_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register16_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register17_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register17_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register17_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register17_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register17_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register18_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register18_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register18_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register18_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register18_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register19_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register19_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register19_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register19_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register19_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register1_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register1_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register1_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register1_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register1_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register20_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register20_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register20_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register20_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register20_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register21_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register21_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register21_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register21_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register21_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register22_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register22_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register22_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register22_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register22_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register23_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register23_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register23_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register23_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register23_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register24_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register24_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register24_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register24_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register24_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register25_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register25_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register25_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register25_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register25_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register26_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register26_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register26_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register26_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register26_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register27_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register27_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register27_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register27_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register27_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register2_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register2_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register2_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register2_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register2_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register3_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register3_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register3_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register3_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register3_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register4_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register4_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register4_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register4_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register4_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register5_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register5_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register5_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register5_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register5_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register6_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register6_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register6_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register6_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register6_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register7_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register7_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register7_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register7_data_in' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register7_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register8_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register8_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register8_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register8_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register8_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register9_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register9_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register9_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register9_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register9_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register_ce' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register_clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register_clr' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.to_register_data_in' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'sysgen_dut.to_register_en' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.user_int_1o' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.user_int_2o' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.user_int_3o' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register1.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register10.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register11.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register12.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register13.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register14.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register15.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register16.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register17.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register18.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register19.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register2.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register20.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register21.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register22.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register23.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register24.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register25.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register26.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register27.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register3.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register4.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register5.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register6.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register7.dout' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'to_register8.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
    'to_register9.dout' => {
      'hdlType' => 'std_logic_vector(31 downto 0)',
      'width' => 32,
    },
  },
  'subblocks' => {
    'bram_rd_addr' => {
      'connections' => {
        'bram_rd_addr' => 'sysgen_dut.bram_rd_addr',
      },
      'entity' => {
        'attributes' => {
          'entityAlreadyNetlisted' => 1,
          'isGateway' => 1,
          'is_floating_block' => 1,
        },
        'entityName' => 'bram_rd_addr',
        'ports' => {
          'bram_rd_addr' => {
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        'bram_wr_en' => 'sysgen_dut.bram_wr_en',
        'clk' => '.clk',
        'fifo_rd_count' => '.fifo_rd_count',
        'fifo_rd_dout' => '.fifo_rd_dout',
        'fifo_rd_empty' => '.fifo_rd_empty',
        'fifo_rd_en' => 'sysgen_dut.fifo_rd_en',
        'fifo_rd_pempty' => '.fifo_rd_pempty',
        'fifo_rd_valid' => '.fifo_rd_valid',
        'fifo_wr_count' => '.fifo_wr_count',
        'fifo_wr_din' => 'sysgen_dut.fifo_wr_din',
        'fifo_wr_en' => 'sysgen_dut.fifo_wr_en',
        'fifo_wr_full' => '.fifo_wr_full',
        'fifo_wr_pfull' => '.fifo_wr_pfull',
        'from_register10_data_out' => 'from_register10.data_out',
        'from_register11_data_out' => 'from_register11.data_out',
        'from_register12_data_out' => 'from_register12.data_out',
        'from_register13_data_out' => 'from_register13.data_out',
        'from_register14_data_out' => 'from_register14.data_out',
        'from_register15_data_out' => 'from_register15.data_out',
        'from_register16_data_out' => 'from_register16.data_out',
        'from_register17_data_out' => 'from_register17.data_out',
        'from_register18_data_out' => 'from_register18.data_out',
        'from_register19_data_out' => 'from_register19.data_out',
        'from_register1_data_out' => 'from_register1.data_out',
        'from_register20_data_out' => 'from_register20.data_out',
        'from_register21_data_out' => 'from_register21.data_out',
        'from_register22_data_out' => 'from_register22.data_out',
        'from_register23_data_out' => 'from_register23.data_out',
        'from_register24_data_out' => 'from_register24.data_out',
        'from_register25_data_out' => 'from_register25.data_out',
        'from_register26_data_out' => 'from_register26.data_out',
        'from_register27_data_out' => 'from_register27.data_out',
        'from_register28_data_out' => 'from_register28.data_out',
        'from_register29_data_out' => 'from_register29.data_out',
        'from_register2_data_out' => 'from_register2.data_out',
        'from_register30_data_out' => 'from_register30.data_out',
        'from_register31_data_out' => 'from_register31.data_out',
        'from_register32_data_out' => 'from_register32.data_out',
        'from_register33_data_out' => 'from_register33.data_out',
        'from_register3_data_out' => 'from_register3.data_out',
        'from_register4_data_out' => 'from_register4.data_out',
        'from_register5_data_out' => 'from_register5.data_out',
        'from_register6_data_out' => 'from_register6.data_out',
        'from_register7_data_out' => 'from_register7.data_out',
        'from_register8_data_out' => 'from_register8.data_out',
        'from_register9_data_out' => 'from_register9.data_out',
        'from_register_data_out' => 'from_register.data_out',
        'rst_i' => '.rst_i',
        'rst_o' => 'sysgen_dut.rst_o',
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
        'to_register10_dout' => 'to_register10.dout',
        'to_register10_en' => 'sysgen_dut.to_register10_en',
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
        'to_register11_dout' => 'to_register11.dout',
        'to_register11_en' => 'sysgen_dut.to_register11_en',
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
        'to_register12_dout' => 'to_register12.dout',
        'to_register12_en' => 'sysgen_dut.to_register12_en',
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
        'to_register13_dout' => 'to_register13.dout',
        'to_register13_en' => 'sysgen_dut.to_register13_en',
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
        'to_register14_dout' => 'to_register14.dout',
        'to_register14_en' => 'sysgen_dut.to_register14_en',
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
        'to_register15_dout' => 'to_register15.dout',
        'to_register15_en' => 'sysgen_dut.to_register15_en',
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
        'to_register16_dout' => 'to_register16.dout',
        'to_register16_en' => 'sysgen_dut.to_register16_en',
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
        'to_register17_dout' => 'to_register17.dout',
        'to_register17_en' => 'sysgen_dut.to_register17_en',
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
        'to_register18_dout' => 'to_register18.dout',
        'to_register18_en' => 'sysgen_dut.to_register18_en',
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
        'to_register19_dout' => 'to_register19.dout',
        'to_register19_en' => 'sysgen_dut.to_register19_en',
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
        'to_register1_dout' => 'to_register1.dout',
        'to_register1_en' => 'sysgen_dut.to_register1_en',
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
        'to_register20_dout' => 'to_register20.dout',
        'to_register20_en' => 'sysgen_dut.to_register20_en',
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
        'to_register21_dout' => 'to_register21.dout',
        'to_register21_en' => 'sysgen_dut.to_register21_en',
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
        'to_register22_dout' => 'to_register22.dout',
        'to_register22_en' => 'sysgen_dut.to_register22_en',
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
        'to_register23_dout' => 'to_register23.dout',
        'to_register23_en' => 'sysgen_dut.to_register23_en',
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
        'to_register24_dout' => 'to_register24.dout',
        'to_register24_en' => 'sysgen_dut.to_register24_en',
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
        'to_register25_dout' => 'to_register25.dout',
        'to_register25_en' => 'sysgen_dut.to_register25_en',
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
        'to_register26_dout' => 'to_register26.dout',
        'to_register26_en' => 'sysgen_dut.to_register26_en',
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
        'to_register27_dout' => 'to_register27.dout',
        'to_register27_en' => 'sysgen_dut.to_register27_en',
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
        'to_register2_dout' => 'to_register2.dout',
        'to_register2_en' => 'sysgen_dut.to_register2_en',
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
        'to_register3_dout' => 'to_register3.dout',
        'to_register3_en' => 'sysgen_dut.to_register3_en',
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
        'to_register4_dout' => 'to_register4.dout',
        'to_register4_en' => 'sysgen_dut.to_register4_en',
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
        'to_register5_dout' => 'to_register5.dout',
        'to_register5_en' => 'sysgen_dut.to_register5_en',
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
        'to_register6_dout' => 'to_register6.dout',
        'to_register6_en' => 'sysgen_dut.to_register6_en',
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
        'to_register7_dout' => 'to_register7.dout',
        'to_register7_en' => 'sysgen_dut.to_register7_en',
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
        'to_register8_dout' => 'to_register8.dout',
        'to_register8_en' => 'sysgen_dut.to_register8_en',
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
        'to_register9_dout' => 'to_register9.dout',
        'to_register9_en' => 'sysgen_dut.to_register9_en',
        'to_register_ce' => 'sysgen_dut.to_register_ce',
        'to_register_clk' => 'sysgen_dut.to_register_clk',
        'to_register_clr' => 'sysgen_dut.to_register_clr',
        'to_register_data_in' => 'sysgen_dut.to_register_data_in',
        'to_register_dout' => 'to_register.dout',
        'to_register_en' => 'sysgen_dut.to_register_en',
        'user_int_1o' => 'sysgen_dut.user_int_1o',
        'user_int_2o' => 'sysgen_dut.user_int_2o',
        'user_int_3o' => 'sysgen_dut.user_int_3o',
      },
      'entity' => {
        'attributes' => {
          'entityAlreadyNetlisted' => 1,
          'hdlArchAttributes' => [
          ],
          'hdlEntityAttributes' => [
          ],
          'isClkWrapper' => 1,
        },
        'connections' => {
          'bram_rd_addr' => 'bram_rd_addr_net',
          'bram_rd_dout' => 'bram_rd_dout_net',
          'bram_wr_addr' => 'bram_wr_addr_net',
          'bram_wr_din' => 'bram_wr_din_net',
          'bram_wr_en' => 'bram_wr_en_net',
          'clk' => 'clkNet',
          'fifo_rd_count' => 'fifo_rd_count_net',
          'fifo_rd_dout' => 'fifo_rd_dout_net',
          'fifo_rd_empty' => 'fifo_rd_empty_net',
          'fifo_rd_en' => 'fifo_rd_en_net',
          'fifo_rd_pempty' => 'fifo_rd_pempty_net',
          'fifo_rd_valid' => 'fifo_rd_valid_net',
          'fifo_wr_count' => 'fifo_wr_count_net',
          'fifo_wr_din' => 'fifo_wr_din_net',
          'fifo_wr_en' => 'fifo_wr_en_net',
          'fifo_wr_full' => 'fifo_wr_full_net',
          'fifo_wr_pfull' => 'fifo_wr_pfull_net',
          'from_register10_data_out' => 'data_out_x1_net',
          'from_register11_data_out' => 'data_out_x2_net',
          'from_register12_data_out' => 'data_out_x3_net',
          'from_register13_data_out' => 'data_out_x4_net',
          'from_register14_data_out' => 'data_out_x5_net',
          'from_register15_data_out' => 'from_register15_data_out_net',
          'from_register16_data_out' => 'from_register16_data_out_net',
          'from_register17_data_out' => 'data_out_x8_net',
          'from_register18_data_out' => 'data_out_x9_net',
          'from_register19_data_out' => 'from_register19_data_out_net',
          'from_register1_data_out' => 'from_register1_data_out_net',
          'from_register20_data_out' => 'data_out_x12_net',
          'from_register21_data_out' => 'data_out_x13_net',
          'from_register22_data_out' => 'data_out_x14_net',
          'from_register23_data_out' => 'data_out_x15_net',
          'from_register24_data_out' => 'data_out_x16_net',
          'from_register25_data_out' => 'data_out_x17_net',
          'from_register26_data_out' => 'data_out_x18_net',
          'from_register27_data_out' => 'data_out_x19_net',
          'from_register28_data_out' => 'data_out_x20_net',
          'from_register29_data_out' => 'data_out_x21_net',
          'from_register2_data_out' => 'from_register2_data_out_net',
          'from_register30_data_out' => 'data_out_x23_net',
          'from_register31_data_out' => 'data_out_x24_net',
          'from_register32_data_out' => 'data_out_x25_net',
          'from_register33_data_out' => 'data_out_x26_net',
          'from_register3_data_out' => 'data_out_x22_net',
          'from_register4_data_out' => 'data_out_x27_net',
          'from_register5_data_out' => 'data_out_x28_net',
          'from_register6_data_out' => 'data_out_x29_net',
          'from_register7_data_out' => 'data_out_x30_net',
          'from_register8_data_out' => 'data_out_x31_net',
          'from_register9_data_out' => 'data_out_x32_net',
          'from_register_data_out' => 'from_register_data_out_net',
          'rst_i' => 'rst_i_net',
          'rst_o' => 'rst_o_net',
          'to_register10_ce' => 'ce_1_sg_x0',
          'to_register10_clk' => 'clk_1_sg_x0',
          'to_register10_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register10_data_in' => 'data_in_x1_net',
          'to_register10_dout' => 'to_register10_dout_net',
          'to_register10_en' => 'constant6_op_net_x2',
          'to_register11_ce' => 'ce_1_sg_x0',
          'to_register11_clk' => 'clk_1_sg_x0',
          'to_register11_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register11_data_in' => 'data_in_x2_net',
          'to_register11_dout' => 'to_register11_dout_net',
          'to_register11_en' => 'constant6_op_net_x3',
          'to_register12_ce' => 'ce_1_sg_x0',
          'to_register12_clk' => 'clk_1_sg_x0',
          'to_register12_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register12_data_in' => 'data_in_x3_net',
          'to_register12_dout' => 'to_register12_dout_net',
          'to_register12_en' => 'constant6_op_net_x4',
          'to_register13_ce' => 'ce_1_sg_x0',
          'to_register13_clk' => 'clk_1_sg_x0',
          'to_register13_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register13_data_in' => 'data_in_x4_net',
          'to_register13_dout' => 'to_register13_dout_net',
          'to_register13_en' => 'constant6_op_net_x5',
          'to_register14_ce' => 'ce_1_sg_x0',
          'to_register14_clk' => 'clk_1_sg_x0',
          'to_register14_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register14_data_in' => 'data_in_x5_net',
          'to_register14_dout' => 'to_register14_dout_net',
          'to_register14_en' => 'constant6_op_net_x6',
          'to_register15_ce' => 'ce_1_sg_x0',
          'to_register15_clk' => 'clk_1_sg_x0',
          'to_register15_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register15_data_in' => 'data_in_x6_net',
          'to_register15_dout' => 'to_register15_dout_net',
          'to_register15_en' => 'constant6_op_net_x7',
          'to_register16_ce' => 'ce_1_sg_x0',
          'to_register16_clk' => 'clk_1_sg_x0',
          'to_register16_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register16_data_in' => 'data_in_x7_net',
          'to_register16_dout' => 'to_register16_dout_net',
          'to_register16_en' => 'constant6_op_net_x8',
          'to_register17_ce' => 'ce_1_sg_x0',
          'to_register17_clk' => 'clk_1_sg_x0',
          'to_register17_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register17_data_in' => 'data_in_x8_net',
          'to_register17_dout' => 'to_register17_dout_net',
          'to_register17_en' => 'constant6_op_net_x9',
          'to_register18_ce' => 'ce_1_sg_x0',
          'to_register18_clk' => 'clk_1_sg_x0',
          'to_register18_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register18_data_in' => 'data_in_x9_net',
          'to_register18_dout' => 'to_register18_dout_net',
          'to_register18_en' => 'constant6_op_net_x10',
          'to_register19_ce' => 'ce_1_sg_x0',
          'to_register19_clk' => 'clk_1_sg_x0',
          'to_register19_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register19_data_in' => 'data_in_x10_net',
          'to_register19_dout' => 'to_register19_dout_net',
          'to_register19_en' => 'constant6_op_net_x11',
          'to_register1_ce' => 'ce_1_sg_x0',
          'to_register1_clk' => 'clk_1_sg_x0',
          'to_register1_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register1_data_in' => 'data_in_x0_net',
          'to_register1_dout' => 'to_register1_dout_net',
          'to_register1_en' => 'constant6_op_net_x1',
          'to_register20_ce' => 'ce_1_sg_x0',
          'to_register20_clk' => 'clk_1_sg_x0',
          'to_register20_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register20_data_in' => 'data_in_x12_net',
          'to_register20_dout' => 'to_register20_dout_net',
          'to_register20_en' => 'constant6_op_net_x13',
          'to_register21_ce' => 'ce_1_sg_x0',
          'to_register21_clk' => 'clk_1_sg_x0',
          'to_register21_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register21_data_in' => 'data_in_x13_net',
          'to_register21_dout' => 'to_register21_dout_net',
          'to_register21_en' => 'constant6_op_net_x14',
          'to_register22_ce' => 'ce_1_sg_x0',
          'to_register22_clk' => 'clk_1_sg_x0',
          'to_register22_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register22_data_in' => 'data_in_x14_net',
          'to_register22_dout' => 'to_register22_dout_net',
          'to_register22_en' => 'constant6_op_net_x15',
          'to_register23_ce' => 'ce_1_sg_x0',
          'to_register23_clk' => 'clk_1_sg_x0',
          'to_register23_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register23_data_in' => 'data_in_x15_net',
          'to_register23_dout' => 'to_register23_dout_net',
          'to_register23_en' => 'constant6_op_net_x16',
          'to_register24_ce' => 'ce_1_sg_x0',
          'to_register24_clk' => 'clk_1_sg_x0',
          'to_register24_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register24_data_in' => 'data_in_x16_net',
          'to_register24_dout' => 'to_register24_dout_net',
          'to_register24_en' => 'constant6_op_net_x17',
          'to_register25_ce' => 'ce_1_sg_x0',
          'to_register25_clk' => 'clk_1_sg_x0',
          'to_register25_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register25_data_in' => 'data_in_x17_net',
          'to_register25_dout' => 'to_register25_dout_net',
          'to_register25_en' => 'constant6_op_net_x18',
          'to_register26_ce' => 'ce_1_sg_x0',
          'to_register26_clk' => 'clk_1_sg_x0',
          'to_register26_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register26_data_in' => 'data_in_x18_net',
          'to_register26_dout' => 'to_register26_dout_net',
          'to_register26_en' => 'constant6_op_net_x19',
          'to_register27_ce' => 'ce_1_sg_x0',
          'to_register27_clk' => 'clk_1_sg_x0',
          'to_register27_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register27_data_in' => 'data_in_x19_net',
          'to_register27_dout' => 'to_register27_dout_net',
          'to_register27_en' => 'constant6_op_net_x20',
          'to_register2_ce' => 'ce_1_sg_x0',
          'to_register2_clk' => 'clk_1_sg_x0',
          'to_register2_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register2_data_in' => 'data_in_x11_net',
          'to_register2_dout' => 'to_register2_dout_net',
          'to_register2_en' => 'constant6_op_net_x12',
          'to_register3_ce' => 'ce_1_sg_x0',
          'to_register3_clk' => 'clk_1_sg_x0',
          'to_register3_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register3_data_in' => 'data_in_x20_net',
          'to_register3_dout' => 'to_register3_dout_net',
          'to_register3_en' => 'constant6_op_net_x21',
          'to_register4_ce' => 'ce_1_sg_x0',
          'to_register4_clk' => 'clk_1_sg_x0',
          'to_register4_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register4_data_in' => 'data_in_x21_net',
          'to_register4_dout' => 'to_register4_dout_net',
          'to_register4_en' => 'constant6_op_net_x22',
          'to_register5_ce' => 'ce_1_sg_x0',
          'to_register5_clk' => 'clk_1_sg_x0',
          'to_register5_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register5_data_in' => 'data_in_x22_net',
          'to_register5_dout' => 'to_register5_dout_net',
          'to_register5_en' => 'constant6_op_net_x23',
          'to_register6_ce' => 'ce_1_sg_x0',
          'to_register6_clk' => 'clk_1_sg_x0',
          'to_register6_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register6_data_in' => 'data_in_x23_net',
          'to_register6_dout' => 'to_register6_dout_net',
          'to_register6_en' => 'constant6_op_net_x24',
          'to_register7_ce' => 'ce_1_sg_x0',
          'to_register7_clk' => 'clk_1_sg_x0',
          'to_register7_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register7_data_in' => 'data_in_x24_net',
          'to_register7_dout' => 'to_register7_dout_net',
          'to_register7_en' => 'constant6_op_net_x25',
          'to_register8_ce' => 'ce_1_sg_x0',
          'to_register8_clk' => 'clk_1_sg_x0',
          'to_register8_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register8_data_in' => 'data_in_x25_net',
          'to_register8_dout' => 'to_register8_dout_net',
          'to_register8_en' => 'constant6_op_net_x26',
          'to_register9_ce' => 'ce_1_sg_x0',
          'to_register9_clk' => 'clk_1_sg_x0',
          'to_register9_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register9_data_in' => 'data_in_x26_net',
          'to_register9_dout' => 'to_register9_dout_net',
          'to_register9_en' => 'constant6_op_net_x27',
          'to_register_ce' => 'ce_1_sg_x0',
          'to_register_clk' => 'clk_1_sg_x0',
          'to_register_clr' => [
            'constant',
            '\'0\'',
          ],
          'to_register_data_in' => 'data_in_net',
          'to_register_dout' => 'to_register_dout_net',
          'to_register_en' => 'constant6_op_net_x0',
          'user_int_1o' => 'user_int_1o_net',
          'user_int_2o' => 'user_int_2o_net',
          'user_int_3o' => 'user_int_3o_net',
        },
        'entityName' => 'user_logic_cw',
        'nets' => {
          'bram_rd_addr_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(11 downto 0)',
            'width' => 12,
          },
          'bram_rd_dout_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(63 downto 0)',
            'width' => 64,
          },
          'bram_wr_addr_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(11 downto 0)',
            'width' => 12,
          },
          'bram_wr_din_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(63 downto 0)',
            'width' => 64,
          },
          'bram_wr_en_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(7 downto 0)',
            'width' => 8,
          },
          'ce_1_sg_x0' => {
            'attributes' => {
              'hdlNetAttributes' => [
                [
                  'MAX_FANOUT',
                  'string',
                  '"REDUCE"',
                ],
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clkNet' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clk_1_sg_x0' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x0' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x1' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x10' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x11' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x12' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x13' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x14' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x15' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x16' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x17' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x18' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x19' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x2' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x20' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x21' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x22' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x23' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x24' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x25' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x26' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x27' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x3' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x4' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x5' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x6' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x7' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x8' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'constant6_op_net_x9' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x0_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x10_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x11_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x12_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x13_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x14_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x15_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x16_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x17_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x18_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x19_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x1_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x20_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x21_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x22_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x23_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x24_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x25_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x26_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x2_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x3_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x4_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x5_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x6_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x7_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_in_x8_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_in_x9_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_out_x12_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_out_x13_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_out_x14_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_out_x15_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_out_x16_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'data_out_x17_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'data_out_x18_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
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            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'fifo_rd_valid' => {
            'attributes' => {
              'bin_pt' => 0,
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_valid.dat',
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_valid/FIFO_rd_valid',
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              'timingConstraint' => 'none',
              'type' => 'Bool',
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            'direction' => 'in',
            'hdlType' => 'std_logic',
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          'fifo_wr_count' => {
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              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_count.dat',
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              'timingConstraint' => 'none',
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            'direction' => 'in',
            'hdlType' => 'std_logic_vector(14 downto 0)',
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          'fifo_wr_din' => {
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              'bin_pt' => 0,
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_din.dat',
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              'timingConstraint' => 'none',
              'type' => 'UFix_72_0',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic_vector(71 downto 0)',
            'width' => 72,
          },
          'fifo_wr_en' => {
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            'direction' => 'out',
            'hdlType' => 'std_logic',
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          'fifo_wr_full' => {
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              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_full.dat',
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            'direction' => 'in',
            'hdlType' => 'std_logic',
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          'fifo_wr_pfull' => {
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            'direction' => 'in',
            'hdlType' => 'std_logic',
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          'from_register10_data_out' => {
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              'must_be_hdl_vector' => 1,
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          'from_register11_data_out' => {
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              'must_be_hdl_vector' => 1,
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            'hdlType' => 'std_logic_vector(31 downto 0)',
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          'from_register12_data_out' => {
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register12/data_out',
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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          'from_register13_data_out' => {
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register13/data_out',
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            'direction' => 'in',
            'hdlType' => 'std_logic_vector(31 downto 0)',
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          'from_register14_data_out' => {
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register14/data_out',
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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          'from_register15_data_out' => {
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              'must_be_hdl_vector' => 1,
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            'direction' => 'in',
            'hdlType' => 'std_logic_vector(0 downto 0)',
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          'from_register16_data_out' => {
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register16/data_out',
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            'direction' => 'in',
            'hdlType' => 'std_logic_vector(0 downto 0)',
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          'from_register17_data_out' => {
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register17/data_out',
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            'direction' => 'in',
            'hdlType' => 'std_logic_vector(31 downto 0)',
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          'from_register18_data_out' => {
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register18/data_out',
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            'direction' => 'in',
            'hdlType' => 'std_logic_vector(0 downto 0)',
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          'from_register19_data_out' => {
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            'direction' => 'in',
            'hdlType' => 'std_logic_vector(31 downto 0)',
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          'from_register1_data_out' => {
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              'must_be_hdl_vector' => 1,
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          'from_register20_data_out' => {
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          'from_register21_data_out' => {
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          'from_register22_data_out' => {
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          'from_register23_data_out' => {
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          'from_register26_data_out' => {
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          'from_register31_data_out' => {
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          'from_register32_data_out' => {
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              'inputFile' => 'pcie_userlogic_00_user_logic_rst_i.dat',
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              'type' => 'Bool',
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            'direction' => 'in',
            'hdlType' => 'std_logic',
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              'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
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            'attributes' => {
              'bin_pt' => 0,
              'is_floating_block' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 1,
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/en',
              'type' => 'Bool',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic_vector(0 downto 0)',
            'width' => 1,
          },
          'to_register_ce' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isCe' => 1,
              'is_floating_block' => 1,
              'period' => 1,
              'type' => 'logic',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'to_register_clk' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isClk' => 1,
              'is_floating_block' => 1,
              'period' => 1,
              'type' => 'logic',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'to_register_clr' => {
            'attributes' => {
              'domain' => '',
              'group' => 1,
              'isClr' => 1,
              'is_floating_block' => 1,
              'period' => 1,
              'type' => 'logic',
              'valid_bit_used' => 0,
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'to_register_data_in' => {
            'attributes' => {
              'bin_pt' => 0,
              'is_floating_block' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 0,
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/data_in',
              'type' => 'UFix_32_0',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'to_register_dout' => {
            'attributes' => {
              'bin_pt' => 0,
              'is_floating_block' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 0,
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/dout',
              'type' => 'UFix_32_0',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic_vector(31 downto 0)',
            'width' => 32,
          },
          'to_register_en' => {
            'attributes' => {
              'bin_pt' => 0,
              'is_floating_block' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 1,
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/en',
              'type' => 'Bool',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic_vector(0 downto 0)',
            'width' => 1,
          },
          'user_int_1o' => {
            'attributes' => {
              'bin_pt' => 0,
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 0,
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
              'timingConstraint' => 'none',
              'type' => 'Bool',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'user_int_2o' => {
            'attributes' => {
              'bin_pt' => 0,
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 0,
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
              'timingConstraint' => 'none',
              'type' => 'Bool',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'user_int_3o' => {
            'attributes' => {
              'bin_pt' => 0,
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 0,
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
              'timingConstraint' => 'none',
              'type' => 'Bool',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
        },
        'subblocks' => {
          'default_clock_driver_x0' => {
            'connections' => {
              'ce_1' => 'ce_1_sg_x0',
              'clk_1' => 'clk_1_sg_x0',
              'sysce' => [
                'constant',
                '\'1\'',
              ],
              'sysce_clr' => [
                'constant',
                '\'0\'',
              ],
              'sysclk' => 'clkNet',
            },
            'entity' => {
              'attributes' => {
                'domain' => 'default',
                'hdlArchAttributes' => [
                  [
                    'syn_noprune',
                    'boolean',
                    'true',
                  ],
                  [
                    'optimize_primitives',
                    'boolean',
                    'false',
                  ],
                  [
                    'dont_touch',
                    'boolean',
                    'true',
                  ],
                ],
                'hdlEntityAttributes' => [
                ],
                'isClkDriver' => 1,
              },
              'entityName' => 'default_clock_driver',
              'ports' => {
                'ce_1' => {
                  'attributes' => {
                    'domain' => 'default',
                    'group' => 1,
                    'isCe' => 1,
                    'period' => 1,
                    'type' => 'logic',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'clk_1' => {
                  'attributes' => {
                    'domain' => 'default',
                    'group' => 1,
                    'isClk' => 1,
                    'period' => 1,
                    'type' => 'logic',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'sysce' => {
                  'attributes' => {
                    'group' => 6,
                    'isCe' => 1,
                    'period' => 1,
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'sysce_clr' => {
                  'attributes' => {
                    'group' => 6,
                    'isClr' => 1,
                    'period' => 1,
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'sysclk' => {
                  'attributes' => {
                    'group' => 6,
                    'isClk' => 1,
                    'period' => 1,
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
              },
            },
            'entityName' => 'default_clock_driver',
          },
          'persistentdff_inst' => {
            'connections' => {
              'clk' => 'clkNet',
              'd' => 'persistentdff_inst_q',
              'q' => 'persistentdff_inst_q',
            },
            'entity' => {
              'attributes' => {
                'entityAlreadyNetlisted' => 1,
                'hdlCompAttributes' => [
                  [
                    'syn_black_box',
                    'boolean',
                    'true',
                  ],
                  [
                    'box_type',
                    'string',
                    '"black_box"',
                  ],
                ],
                'is_persistent_dff' => 1,
                'needsComponentDeclaration' => 1,
              },
              'entityName' => 'xlpersistentdff',
              'ports' => {
                'clk' => {
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'd' => {
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'q' => {
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
              },
            },
            'entityName' => 'xlpersistentdff',
          },
          'user_logic_x0' => {
            'connections' => {
              'bram_rd_addr' => 'bram_rd_addr_net',
              'bram_rd_dout' => 'bram_rd_dout_net',
              'bram_wr_addr' => 'bram_wr_addr_net',
              'bram_wr_din' => 'bram_wr_din_net',
              'bram_wr_en' => 'bram_wr_en_net',
              'ce_1' => 'ce_1_sg_x0',
              'clk_1' => 'clk_1_sg_x0',
              'data_in' => 'data_in_net',
              'data_in_x0' => 'data_in_x0_net',
              'data_in_x1' => 'data_in_x1_net',
              'data_in_x10' => 'data_in_x10_net',
              'data_in_x11' => 'data_in_x11_net',
              'data_in_x12' => 'data_in_x12_net',
              'data_in_x13' => 'data_in_x13_net',
              'data_in_x14' => 'data_in_x14_net',
              'data_in_x15' => 'data_in_x15_net',
              'data_in_x16' => 'data_in_x16_net',
              'data_in_x17' => 'data_in_x17_net',
              'data_in_x18' => 'data_in_x18_net',
              'data_in_x19' => 'data_in_x19_net',
              'data_in_x2' => 'data_in_x2_net',
              'data_in_x20' => 'data_in_x20_net',
              'data_in_x21' => 'data_in_x21_net',
              'data_in_x22' => 'data_in_x22_net',
              'data_in_x23' => 'data_in_x23_net',
              'data_in_x24' => 'data_in_x24_net',
              'data_in_x25' => 'data_in_x25_net',
              'data_in_x26' => 'data_in_x26_net',
              'data_in_x3' => 'data_in_x3_net',
              'data_in_x4' => 'data_in_x4_net',
              'data_in_x5' => 'data_in_x5_net',
              'data_in_x6' => 'data_in_x6_net',
              'data_in_x7' => 'data_in_x7_net',
              'data_in_x8' => 'data_in_x8_net',
              'data_in_x9' => 'data_in_x9_net',
              'data_out_x1' => 'data_out_x1_net',
              'data_out_x12' => 'data_out_x12_net',
              'data_out_x13' => 'data_out_x13_net',
              'data_out_x14' => 'data_out_x14_net',
              'data_out_x15' => 'data_out_x15_net',
              'data_out_x16' => 'data_out_x16_net',
              'data_out_x17' => 'data_out_x17_net',
              'data_out_x18' => 'data_out_x18_net',
              'data_out_x19' => 'data_out_x19_net',
              'data_out_x2' => 'data_out_x2_net',
              'data_out_x20' => 'data_out_x20_net',
              'data_out_x21' => 'data_out_x21_net',
              'data_out_x22' => 'data_out_x22_net',
              'data_out_x23' => 'data_out_x23_net',
              'data_out_x24' => 'data_out_x24_net',
              'data_out_x25' => 'data_out_x25_net',
              'data_out_x26' => 'data_out_x26_net',
              'data_out_x27' => 'data_out_x27_net',
              'data_out_x28' => 'data_out_x28_net',
              'data_out_x29' => 'data_out_x29_net',
              'data_out_x3' => 'data_out_x3_net',
              'data_out_x30' => 'data_out_x30_net',
              'data_out_x31' => 'data_out_x31_net',
              'data_out_x32' => 'data_out_x32_net',
              'data_out_x4' => 'data_out_x4_net',
              'data_out_x5' => 'data_out_x5_net',
              'data_out_x8' => 'data_out_x8_net',
              'data_out_x9' => 'data_out_x9_net',
              'en' => 'constant6_op_net_x0',
              'en_x0' => 'constant6_op_net_x1',
              'en_x1' => 'constant6_op_net_x2',
              'en_x10' => 'constant6_op_net_x11',
              'en_x11' => 'constant6_op_net_x12',
              'en_x12' => 'constant6_op_net_x13',
              'en_x13' => 'constant6_op_net_x14',
              'en_x14' => 'constant6_op_net_x15',
              'en_x15' => 'constant6_op_net_x16',
              'en_x16' => 'constant6_op_net_x17',
              'en_x17' => 'constant6_op_net_x18',
              'en_x18' => 'constant6_op_net_x19',
              'en_x19' => 'constant6_op_net_x20',
              'en_x2' => 'constant6_op_net_x3',
              'en_x20' => 'constant6_op_net_x21',
              'en_x21' => 'constant6_op_net_x22',
              'en_x22' => 'constant6_op_net_x23',
              'en_x23' => 'constant6_op_net_x24',
              'en_x24' => 'constant6_op_net_x25',
              'en_x25' => 'constant6_op_net_x26',
              'en_x26' => 'constant6_op_net_x27',
              'en_x3' => 'constant6_op_net_x4',
              'en_x4' => 'constant6_op_net_x5',
              'en_x5' => 'constant6_op_net_x6',
              'en_x6' => 'constant6_op_net_x7',
              'en_x7' => 'constant6_op_net_x8',
              'en_x8' => 'constant6_op_net_x9',
              'en_x9' => 'constant6_op_net_x10',
              'fifo_rd_count_x0' => 'fifo_rd_count_net',
              'fifo_rd_dout' => 'fifo_rd_dout_net',
              'fifo_rd_empty' => 'fifo_rd_empty_net',
              'fifo_rd_en_x1' => 'fifo_rd_en_net',
              'fifo_rd_pempty_x0' => 'fifo_rd_pempty_net',
              'fifo_rd_valid' => 'fifo_rd_valid_net',
              'fifo_wr_count_x0' => 'fifo_wr_count_net',
              'fifo_wr_din' => 'fifo_wr_din_net',
              'fifo_wr_en_x0' => 'fifo_wr_en_net',
              'fifo_wr_full_x0' => 'fifo_wr_full_net',
              'fifo_wr_pfull_x0' => 'fifo_wr_pfull_net',
              'rst_i' => 'rst_i_net',
              'rst_o' => 'rst_o_net',
              'user_int_1o' => 'user_int_1o_net',
              'user_int_2o' => 'user_int_2o_net',
              'user_int_3o' => 'user_int_3o_net',
            },
            'entity' => {
              'attributes' => {
                'entityAlreadyNetlisted' => 1,
                'hdlKind' => 'vhdl',
                'isDesign' => 1,
                'simulinkName' => 'USER_LOGIC',
              },
              'entityName' => 'user_logic',
              'ports' => {
                'bram_rd_addr' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
                    'is_floating_block' => 1,
                    'is_gateway_port' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 15,
                    'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
                    'source_block' => 'USER_LOGIC',
                    'timingConstraint' => 'none',
                    'type' => 'UFix_12_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(11 downto 0)',
                  'width' => 12,
                },
                'bram_rd_dout' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
                    'is_floating_block' => 1,
                    'is_gateway_port' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 0,
                    'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
                    'source_block' => 'USER_LOGIC',
                    'timingConstraint' => 'none',
                    'type' => 'UFix_64_0',
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic_vector(63 downto 0)',
                  'width' => 64,
                },
                'bram_wr_addr' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
                    'is_floating_block' => 1,
                    'is_gateway_port' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 16,
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
                    'source_block' => 'USER_LOGIC',
                    'timingConstraint' => 'none',
                    'type' => 'UFix_12_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(11 downto 0)',
                  'width' => 12,
                },
                'bram_wr_din' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
                    'is_floating_block' => 1,
                    'is_gateway_port' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 18,
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
                    'source_block' => 'USER_LOGIC',
                    'timingConstraint' => 'none',
                    'type' => 'UFix_64_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(63 downto 0)',
                  'width' => 64,
                },
                'bram_wr_en' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
                    'is_floating_block' => 1,
                    'is_gateway_port' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 23,
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
                    'source_block' => 'USER_LOGIC',
                    'timingConstraint' => 'none',
                    'type' => 'UFix_8_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(7 downto 0)',
                  'width' => 8,
                },
                'ce_1' => {
                  'attributes' => {
                    'domain' => '',
                    'group' => 1,
                    'isCe' => 1,
                    'is_subsys_port' => 1,
                    'period' => 1,
                    'subsys_port_index' => 0,
                    'type' => 'logic',
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'clk_1' => {
                  'attributes' => {
                    'domain' => '',
                    'group' => 1,
                    'isClk' => 1,
                    'is_subsys_port' => 1,
                    'period' => 1,
                    'subsys_port_index' => 0,
                    'type' => 'logic',
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'data_in' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'is_floating_block' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 17,
                    'simulinkName' => 'USER_LOGIC/tx_en_in2',
                    'type' => 'UFix_32_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(31 downto 0)',
                  'width' => 32,
                },
                'data_in_x0' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'is_floating_block' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 1,
                    'simulinkName' => 'USER_LOGIC/tx_en_in1',
                    'type' => 'Bool',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'data_in_x1' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'is_floating_block' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 36,
                    'simulinkName' => 'USER_LOGIC/tx_en_in96',
                    'type' => 'Bool',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'data_in_x10' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'is_floating_block' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 33,
                    'simulinkName' => 'USER_LOGIC/tx_en_in91',
                    'type' => 'UFix_32_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(31 downto 0)',
                  'width' => 32,
                },
                'data_in_x11' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'is_floating_block' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 21,
                    'simulinkName' => 'USER_LOGIC/tx_en_in33',
                    'type' => 'UFix_32_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(31 downto 0)',
                  'width' => 32,
                },
                'data_in_x12' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'is_floating_block' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 6,
                    'simulinkName' => 'USER_LOGIC/tx_en_in113',
                    'type' => 'Bool',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'data_in_x13' => {
                  'attributes' => {
                    'bin_pt' => 0,
                    'is_floating_block' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 8,
                    'simulinkName' => 'USER_LOGIC/tx_en_in115',
                    'type' => 'UFix_32_0',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(31 downto 0)',
                  'width' => 32,
                },
                'data_in_x14' => {
                  'attributes' => {
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