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URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [synth_model/] [globals] - Rev 13

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{
  'XILINX' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
  'clkWrapper' => 'user_logic_cw',
  'clkWrapperFile' => 'user_logic_cw.vhd',
  'createTestbench' => 0,
  'design' => 'user_logic',
  'designFileList' => [
    'user_logic.vhd',
    'user_logic_cw.vhd',
  ],
  'device' => 'xc6vlx240t-1ff1156',
  'family' => 'virtex6',
  'files' => [
    'cntr_11_0_341fbb8cfa0e669e.ngc',
    'icon_1_06_a_87e2f476e984e565.ngc',
    'ila_1_05_a_b6735eb4b876dee5.ngc',
    'xlpersistentdff.ngc',
    'synopsis',
    'user_logic.vhd',
    'xlpersistentdff.ngc',
    'user_logic_cw.vhd',
    'user_logic_cw.ucf',
    'user_logic_cw.xcf',
    'user_logic_cw.sdc',
    'xst_user_logic.prj',
    'xst_user_logic.scr',
    'vcom.do',
    'isim_user_logic.prj',
  ],
  'hdlKind' => 'vhdl',
  'isCombinatorial' => 0,
  'synthesisTool' => 'XST',
  'sysgen' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
  'systemClockPeriod' => 5,
  'testbench' => 0,
  'using71Netlister' => 1,
  'vsimtime' => '11000000275.000000 ns',
}

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