Subversion Repositories pcie_sg_dma

Release 13.3 - xst O.76xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> 
Reading constraint file user_logic_cw.xcf.
XCF parsing done.

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "xst_user_logic.prj"
Input Format                       : mixed
Synthesis Constraint File          : user_logic_cw.xcf

---- Target Parameters
Output File Name                   : "user_logic_cw.ngc"
Output Format                      : NGC
Target Device                      : xc6vlx240t-1ff1156

---- Source Options
Entity Name                        : user_logic_cw
Top Module Name                    : user_logic_cw
Automatic Register Balancing       : no

---- Target Options
Add IO Buffers                     : NO
Pack IO Registers into IOBs        : Auto

---- General Options
Keep Hierarchy                     : NO
Bus Delimiter                      : ()
Hierarchy Separator                : /
Write Timing Constraints           : yes

---- Other Options
report_timing_constraint_problems  : warning

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Goal                  : SPEED

=========================================================================

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" into library work
Parsing entity <cntr_11_0_341fbb8cfa0e669e>.
Parsing architecture <cntr_11_0_341fbb8cfa0e669e_a> of entity <cntr_11_0_341fbb8cfa0e669e>.
Parsing entity <icon_1_06_a_87e2f476e984e565>.
Parsing architecture <icon_1_06_a_87e2f476e984e565_a> of entity <icon_1_06_a_87e2f476e984e565>.
Parsing entity <ila_1_05_a_b6735eb4b876dee5>.
Parsing architecture <ila_1_05_a_b6735eb4b876dee5_a> of entity <ila_1_05_a_b6735eb4b876dee5>.
Parsing package <conv_pkg>.
Parsing package body <conv_pkg>.
Parsing entity <srl17e>.
Parsing architecture <structural> of entity <srl17e>.
Parsing entity <synth_reg>.
Parsing architecture <structural> of entity <synth_reg>.
Parsing entity <synth_reg_reg>.
Parsing architecture <behav> of entity <synth_reg_reg>.
Parsing entity <single_reg_w_init>.
Parsing architecture <structural> of entity <single_reg_w_init>.
Parsing entity <synth_reg_w_init>.
Parsing architecture <structural> of entity <synth_reg_w_init>.
Parsing entity <constant_963ed6358a>.
Parsing architecture <behavior> of entity <constant_963ed6358a>.
Parsing entity <constant_6293007044>.
Parsing architecture <behavior> of entity <constant_6293007044>.
Parsing entity <constant_19562ab42f>.
Parsing architecture <behavior> of entity <constant_19562ab42f>.
Parsing entity <convert_func_call>.
Parsing architecture <behavior> of entity <convert_func_call>.
Parsing entity <xlconvert>.
Parsing architecture <behavior> of entity <xlconvert>.
Parsing entity <xlcounter_free>.
Parsing architecture <behavior> of entity <xlcounter_free>.
Parsing entity <inverter_e5b38cca3b>.
Parsing architecture <behavior> of entity <inverter_e5b38cca3b>.
Parsing entity <logical_80f90b97d0>.
Parsing architecture <behavior> of entity <logical_80f90b97d0>.
Parsing entity <xlregister>.
Parsing architecture <behavior> of entity <xlregister>.
Parsing entity <xlchipscope>.
Parsing architecture <behavior> of entity <xlchipscope>.
Parsing entity <user_logic>.
Parsing architecture <structural> of entity <user_logic>.
Parsing VHDL file "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" into library work
Parsing entity <xlclockdriver>.
Parsing architecture <behavior> of entity <xlclockdriver>.
Parsing entity <default_clock_driver>.
Parsing architecture <structural> of entity <default_clock_driver>.
Parsing entity <user_logic_cw>.
Parsing architecture <structural> of entity <user_logic_cw>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <user_logic_cw> (architecture <structural>) from library <work>.
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 814: Assignment to from_register15_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 815: Assignment to from_register16_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 818: Assignment to from_register19_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 819: Assignment to from_register1_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 830: Assignment to from_register2_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 842: Assignment to from_register_data_out_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 844: Assignment to to_register10_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 845: Assignment to to_register11_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 846: Assignment to to_register12_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 847: Assignment to to_register13_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 848: Assignment to to_register14_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 849: Assignment to to_register15_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 850: Assignment to to_register16_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 851: Assignment to to_register17_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 852: Assignment to to_register18_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 853: Assignment to to_register19_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 854: Assignment to to_register1_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 855: Assignment to to_register20_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 856: Assignment to to_register21_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 857: Assignment to to_register22_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 858: Assignment to to_register23_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 859: Assignment to to_register24_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 860: Assignment to to_register25_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 861: Assignment to to_register26_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 862: Assignment to to_register27_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 863: Assignment to to_register2_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 864: Assignment to to_register3_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 865: Assignment to to_register4_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 866: Assignment to to_register5_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 867: Assignment to to_register6_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 868: Assignment to to_register7_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 869: Assignment to to_register8_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 870: Assignment to to_register9_dout_net ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 871: Assignment to to_register_dout_net ignored, since the identifier is never used

Elaborating entity <default_clock_driver> (architecture <structural>) from library <work>.

Elaborating entity <xlclockdriver> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1898: <fdre> remains a black-box since it has no binding entity.

Elaborating entity <user_logic> (architecture <structural>) from library <work>.

Elaborating entity <xlchipscope> (architecture <behavior>) from library <work>.

Elaborating entity <ila_1_05_a_b6735eb4b876dee5> (architecture <>) from library <work>.

Elaborating entity <icon_1_06_a_87e2f476e984e565> (architecture <>) from library <work>.

Elaborating entity <constant_963ed6358a> (architecture <behavior>) from library <work>.

Elaborating entity <constant_6293007044> (architecture <behavior>) from library <work>.

Elaborating entity <constant_19562ab42f> (architecture <behavior>) from library <work>.

Elaborating entity <xlconvert> (architecture <behavior>) with generics from library <work>.

Elaborating entity <xlcounter_free> (architecture <behavior>) with generics from library <work>.

Elaborating entity <cntr_11_0_341fbb8cfa0e669e> (architecture <>) from library <work>.

Elaborating entity <inverter_e5b38cca3b> (architecture <behavior>) from library <work>.
WARNING:HDLCompiler:871 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2345: Using initial value false for op_mem_22_20_front_din since it is never assigned
WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2351: Assignment to op_mem_22_20_back ignored, since the identifier is never used

Elaborating entity <logical_80f90b97d0> (architecture <behavior>) from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1909: <fdse> remains a black-box since it has no binding entity.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <xlregister> (architecture <behavior>) with generics from library <work>.

Elaborating entity <synth_reg_w_init> (architecture <structural>) with generics from library <work>.

Elaborating entity <single_reg_w_init> (architecture <structural>) with generics from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <user_logic_cw>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".
    Set property "syn_black_box = true" for instance <persistentdff_inst>.
    Set property "syn_noprune = true" for instance <persistentdff_inst>.
    Set property "optimize_primitives = false" for instance <persistentdff_inst>.
    Set property "dont_touch = true" for instance <persistentdff_inst>.
    Set property "MAX_FANOUT = REDUCE" for signal <ce_1_sg_x0>.
    Set property "syn_keep = true" for signal <persistentdff_inst_q>.
    Set property "KEEP = TRUE" for signal <persistentdff_inst_q>.
WARNING:Xst:37 - Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:647 - Input <from_register15_data_out<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register16_data_out<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register19_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register1_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register2_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <from_register_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register10_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register11_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register12_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register13_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register14_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register15_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register16_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register17_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register18_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register19_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register1_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register20_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register21_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register22_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register23_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register24_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register25_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register26_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register27_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register2_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register3_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register4_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register5_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register6_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register7_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register8_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register9_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <to_register_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <user_logic_cw> synthesized.

Synthesizing Unit <default_clock_driver>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".
    Set property "syn_noprune = true".
    Set property "optimize_primitives = false".
    Set property "dont_touch = true".
INFO:Xst:3210 - "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port <clr> of the instance <xlclockdriver> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port <ce_logic> of the instance <xlclockdriver> is unconnected or connected to loadless signal.
    Summary:
        no macro.
Unit <default_clock_driver> synthesized.

Synthesizing Unit <xlclockdriver>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd".
        period = 1
        log_2_period = 1
        pipeline_regs = 5
        use_bufg = 0
    Set property "MAX_FANOUT = REDUCE" for signal <ce_vec>.
    Set property "MAX_FANOUT = REDUCE" for signal <ce_vec_logic>.
INFO:Xst:3210 - "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 254: Output port <o> of the instance <clr_reg> is unconnected or connected to loadless signal.
    Summary:
        no macro.
Unit <xlclockdriver> synthesized.

Synthesizing Unit <synth_reg_w_init_1>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 0
        init_value = "0000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_1> synthesized.

Synthesizing Unit <single_reg_w_init_1>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 0
        init_value = "0000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_1> synthesized.

Synthesizing Unit <user_logic>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
    Summary:
        no macro.
Unit <user_logic> synthesized.

Synthesizing Unit <xlchipscope>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
    Set property "syn_noprune = true".
    Set property "syn_black_box = true" for instance <i_ila>.
    Set property "syn_noprune = true" for instance <i_ila>.
    Set property "syn_black_box = true" for instance <i_icon_for_syn>.
    Set property "syn_noprune = true" for instance <i_icon_for_syn>.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <xlchipscope> synthesized.

Synthesizing Unit <constant_963ed6358a>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <constant_963ed6358a> synthesized.

Synthesizing Unit <constant_6293007044>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <constant_6293007044> synthesized.

Synthesizing Unit <constant_19562ab42f>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <constant_19562ab42f> synthesized.

Synthesizing Unit <xlconvert>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        din_width = 1
        din_bin_pt = 0
        din_arith = 1
        dout_width = 1
        dout_bin_pt = 0
        dout_arith = 1
        en_width = 1
        en_bin_pt = 0
        en_arith = 1
        bool_conversion = 1
        latency = 0
        quantization = 1
        overflow = 1
WARNING:Xst:647 - Input <en<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <xlconvert> synthesized.

Synthesizing Unit <xlcounter_free>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        core_name0 = "cntr_11_0_341fbb8cfa0e669e"
        op_width = 12
        op_arith = 1
    Set property "syn_black_box = true" for instance <comp0.core_instance0>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:647 - Input <up<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <load<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <din<11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <xlcounter_free> synthesized.

Synthesizing Unit <inverter_e5b38cca3b>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <inverter_e5b38cca3b> synthesized.

Synthesizing Unit <logical_80f90b97d0>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
        no macro.
Unit <logical_80f90b97d0> synthesized.

Synthesizing Unit <xlregister_1>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 1
        init_value = "0"
    Summary:
        no macro.
Unit <xlregister_1> synthesized.

Synthesizing Unit <synth_reg_w_init_2>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 2
        init_value = "0"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_2> synthesized.

Synthesizing Unit <single_reg_w_init_2>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 1
        init_index = 2
        init_value = "0"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_2> synthesized.

Synthesizing Unit <xlregister_2>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_2> synthesized.

Synthesizing Unit <synth_reg_w_init_3>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_3> synthesized.

Synthesizing Unit <single_reg_w_init_3>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_3> synthesized.

Synthesizing Unit <xlregister_3>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 12
        init_value = "000000000000"
    Summary:
        no macro.
Unit <xlregister_3> synthesized.

Synthesizing Unit <synth_reg_w_init_4>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 12
        init_index = 2
        init_value = "000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_4> synthesized.

Synthesizing Unit <single_reg_w_init_4>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 12
        init_index = 2
        init_value = "000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_4> synthesized.

Synthesizing Unit <xlregister_4>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000110000110100100011"
    Summary:
        no macro.
Unit <xlregister_4> synthesized.

Synthesizing Unit <synth_reg_w_init_5>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000110000110100100011"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_5> synthesized.

Synthesizing Unit <single_reg_w_init_5>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000110000110100100011"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_5> synthesized.

Synthesizing Unit <xlregister_5>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000000100101011000000"
    Summary:
        no macro.
Unit <xlregister_5> synthesized.

Synthesizing Unit <synth_reg_w_init_6>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000100101011000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_6> synthesized.

Synthesizing Unit <single_reg_w_init_6>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000100101011000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_6> synthesized.

Synthesizing Unit <xlregister_6>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 64
        init_value = "0000000000000000000000000000000000000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_6> synthesized.

Synthesizing Unit <synth_reg_w_init_7>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 64
        init_index = 2
        init_value = "0000000000000000000000000000000000000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_7> synthesized.

Synthesizing Unit <single_reg_w_init_7>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 64
        init_index = 2
        init_value = "0000000000000000000000000000000000000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[32].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[33].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[34].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[35].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[36].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[37].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[38].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[39].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[40].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[41].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[42].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[43].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[44].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[45].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[46].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[47].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[48].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[49].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[50].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[51].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[52].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[53].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[54].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[55].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[56].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[57].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[58].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[59].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[60].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[61].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[62].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[63].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_7> synthesized.

Synthesizing Unit <xlregister_7>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 8
        init_value = "00000000"
    Summary:
        no macro.
Unit <xlregister_7> synthesized.

Synthesizing Unit <synth_reg_w_init_8>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 8
        init_index = 2
        init_value = "00000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_8> synthesized.

Synthesizing Unit <single_reg_w_init_8>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 8
        init_index = 2
        init_value = "00000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_8> synthesized.

Synthesizing Unit <xlregister_8>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 72
        init_value = "000000000000000000000000000000000000000000000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_8> synthesized.

Synthesizing Unit <synth_reg_w_init_9>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 72
        init_index = 2
        init_value = "000000000000000000000000000000000000000000000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_9> synthesized.

Synthesizing Unit <single_reg_w_init_9>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 72
        init_index = 2
        init_value = "000000000000000000000000000000000000000000000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[32].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[33].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[34].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[35].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[36].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[37].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[38].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[39].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[40].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[41].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[42].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[43].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[44].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[45].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[46].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[47].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[48].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[49].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[50].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[51].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[52].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[53].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[54].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[55].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[56].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[57].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[58].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[59].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[60].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[61].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[62].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[63].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[64].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[65].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[66].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[67].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[68].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[69].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[70].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[71].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_9> synthesized.

Synthesizing Unit <xlregister_9>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 15
        init_value = "000000000000000"
    Summary:
        no macro.
Unit <xlregister_9> synthesized.

Synthesizing Unit <synth_reg_w_init_10>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 15
        init_index = 2
        init_value = "000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_10> synthesized.

Synthesizing Unit <single_reg_w_init_10>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 15
        init_index = 2
        init_value = "000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_10> synthesized.

Synthesizing Unit <xlregister_10>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "00000000000000000000000000000001"
    Summary:
        no macro.
Unit <xlregister_10> synthesized.

Synthesizing Unit <synth_reg_w_init_11>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000001"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_11> synthesized.

Synthesizing Unit <single_reg_w_init_11>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "00000000000000000000000000000001"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_11> synthesized.

Synthesizing Unit <xlregister_11>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        d_width = 32
        init_value = "10000000000000000000000000000000"
    Summary:
        no macro.
Unit <xlregister_11> synthesized.

Synthesizing Unit <synth_reg_w_init_12>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "10000000000000000000000000000000"
        latency = 1
    Summary:
        no macro.
Unit <synth_reg_w_init_12> synthesized.

Synthesizing Unit <single_reg_w_init_12>.
    Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic.vhd".
        width = 32
        init_index = 2
        init_value = "10000000000000000000000000000000"
    Set property "syn_black_box = true" for instance <fd_prim_array[0].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[1].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[2].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[3].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[4].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[5].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[6].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[7].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[8].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[9].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[10].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[11].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[12].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[13].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[14].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[15].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[16].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[17].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[18].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[19].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[20].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[21].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[22].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[23].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[24].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[25].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[26].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[27].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[28].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[29].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[30].bit_is_0.fdre_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_black_box = true" for instance <fd_prim_array[31].bit_is_1.fdse_comp>.
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
    Summary:
        no macro.
Unit <single_reg_w_init_12> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <xlpersistentdff.ngc>.
Reading core <ila_1_05_a_b6735eb4b876dee5.ngc>.
Reading core <icon_1_06_a_87e2f476e984e565.ngc>.
Reading core <cntr_11_0_341fbb8cfa0e669e.ngc>.
Loading core <xlpersistentdff> for timing and area information for instance <persistentdff_inst>.
Loading core <ila_1_05_a_b6735eb4b876dee5> for timing and area information for instance <i_ila>.
Loading core <icon_1_06_a_87e2f476e984e565> for timing and area information for instance <i_icon_for_syn>.
Loading core <cntr_11_0_341fbb8cfa0e669e> for timing and area information for instance <comp0.core_instance0>.
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 1329
 Flip-Flops                                            : 1329

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant10> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant11> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant12> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant19> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant20> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant21> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant22> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant23> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant24> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant25> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant26> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant3> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant4> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant7> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant8> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant1>, <constant9> of unit <constant_963ed6358a> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant14>, <constant15> of unit <constant_6293007044> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <user_logic>: instances <constant14>, <constant6> of unit <constant_6293007044> are equivalent, second instance is removed

Optimizing unit <user_logic_cw> ...

Optimizing unit <single_reg_w_init_7> ...

Optimizing unit <single_reg_w_init_3> ...

Optimizing unit <single_reg_w_init_10> ...

Optimizing unit <single_reg_w_init_9> ...

Optimizing unit <single_reg_w_init_4> ...

Optimizing unit <single_reg_w_init_5> ...

Optimizing unit <single_reg_w_init_6> ...

Optimizing unit <single_reg_w_init_8> ...

Optimizing unit <single_reg_w_init_11> ...

Optimizing unit <single_reg_w_init_12> ...

Optimizing unit <user_logic> ...
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
Annotating constraints using XCF file 'user_logic_cw.xcf'
XCF parsing done.
WARNING:Xst:1513 - No elements found for TNM 'D_CLK' on object 'user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_CS_GAND.U_CS_GAND_SRL/I_V6.U_CS_GAND_SRL_V6/I_USE_RPM_EQ0.U_GAND_SRL_SET/CLK_I'.
WARNING:Xst:1513 - No elements found for TNM 'D_CLK' on object 'user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_CS_GAND.U_CS_GAND_SRL/I_V6.U_CS_GAND_SRL_V6/I_USE_RPM_EQ0.U_GAND_SRL_SET/CLK_I'.
WARNING:Xst:1513 - No elements found for TNM 'D_CLK' on object 'user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_CS_GAND.U_CS_GAND_SRL/I_V6.U_CS_GAND_SRL_V6/I_USE_RPM_EQ0.U_GAND_SRL_SET/CLK_I'.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block user_logic_cw, actual ratio is 1.
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[67].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[67].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[66].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[66].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[71].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[71].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[69].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[69].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following 2 FFs/Latches : <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following 7 FFs/Latches : <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in107/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in21/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in109/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in23/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[65].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[65].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[70].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[70].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in108/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in22/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[64].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[64].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[68].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[68].bit_is_0.fdre_comp> 
INFO:Xst:2260 - The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1329
 Flip-Flops                                            : 1329

=========================================================================
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : user_logic_cw.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 617
#      GND                         : 29
#      INV                         : 9
#      LUT1                        : 74
#      LUT2                        : 26
#      LUT3                        : 24
#      LUT4                        : 105
#      LUT5                        : 2
#      LUT6                        : 63
#      MUXCY                       : 11
#      MUXCY_L                     : 149
#      MUXF5                       : 2
#      MUXF6                       : 1
#      MUXF7                       : 9
#      MUXF8                       : 2
#      VCC                         : 37
#      XORCY                       : 74
# FlipFlops/Latches                : 2132
#      FD                          : 370
#      FDC                         : 9
#      FDCE                        : 16
#      FDE                         : 32
#      FDP                         : 196
#      FDR                         : 52
#      FDRE                        : 1411
#      FDS                         : 30
#      FDSE                        : 15
#      LDC                         : 1
# RAMS                             : 6
#      RAMB18E1                    : 1
#      RAMB36E1                    : 5
# Shift Registers                  : 292
#      SRL16                       : 184
#      SRL16E                      : 1
#      SRLC16E                     : 10
#      SRLC32E                     : 97
# Clock Buffers                    : 1
#      BUFG                        : 1
# Others                           : 4
#      BSCAN_VIRTEX6               : 1
#      TIMESPEC                    : 3

Device utilization summary:
---------------------------

Selected Device : 6vlx240tff1156-1 


Slice Logic Utilization: 
 Number of Slice Registers:            2132  out of  301440     0%  
 Number of Slice LUTs:                  595  out of  150720     0%  
    Number used as Logic:               303  out of  150720     0%  
    Number used as Memory:              292  out of  58400     0%  
       Number used as SRL:              292

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   2450
   Number with an unused Flip Flop:     318  out of   2450    12%  
   Number with an unused LUT:          1855  out of   2450    75%  
   Number of fully used LUT-FF pairs:   277  out of   2450    11%  
   Number of unique control sets:        89

IO Utilization: 
 Number of IOs:                        1976
 Number of bonded IOBs:                   0  out of    600     0%  

Specific Feature Utilization:
 Number of Block RAM/FIFO:                6  out of    416     1%  
    Number using Block RAM only:          6
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                                                                                                                              | Clock buffer(FF name)                                                                                                      | Load  |
------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
to_register_clk                                                                                                                           | NONE(default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp)| 2225  |
user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL                                                             | BUFG                                                                                                                       | 209   |
user_logic_x0/chipscope/i_icon_for_syn/CONTROL0(13)(user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O)| NONE(*)(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)                                                  | 1     |
user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT                                                                                     | NONE(user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD)                                                         | 1     |
------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                                                                                                                                                                                                                                                                                                      | Buffer(FF name)                                                                                                                                                                                                                                                                                                                                              | Load  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)| 124   |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)| 124   |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)| 124   |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)| 124   |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)| 124   |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)| 72    |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)| 72    |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)| 72    |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)| 72    |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)| 72    |
user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(user_logic_x0/chipscope/i_ila/XST_VCC:P)                                                                                                                                                                                                                                                                                        | NONE(user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)| 20    |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 5.669ns (Maximum Frequency: 176.398MHz)
   Minimum input arrival time before clock: 1.383ns
   Maximum output required time after clock: 0.375ns
   Maximum combinational path delay: 0.000ns

=========================================================================
Timing constraint: TS_D2_TO_T2 = FROM TIMEGRP "D2_CLK" TO TIMEGRP "FFS" TIG;
  Clock period: 2.394ns (frequency: 417.711MHz)
  Total number of paths / destination ports: 3 / 3
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Delay:                  -2.606ns
  Source:               user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF)
  Destination:          user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
  Data Path Delay:      2.394ns (Levels of Logic = 2)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 0.000ns

  Data Path: user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF) to user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.375   0.587  U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (U0/I_NO_D.U_ILA/U_RST/HALT_pulse)
     LUT3:I0->O            1   0.068   0.417  U0/I_NO_D.U_ILA/U_RST/U_PRST1 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET1)
     LUT4:I3->O            8   0.068   0.445  U0/I_NO_D.U_ILA/U_RST/U_PRST0 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET0)
     FDS:S                     0.434          U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST
    ----------------------------------------
    Total                      2.394ns (0.945ns logic, 1.449ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================
Timing constraint: TS_J2_TO_D2 = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK" TIG;
  Clock period: 2.394ns (frequency: 417.711MHz)
  Total number of paths / destination ports: 1 / 1
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Delay:                  -2.606ns
  Source:               user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF)
  Destination:          user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
  Data Path Delay:      2.394ns (Levels of Logic = 2)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 0.000ns

  Data Path: user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF) to user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.375   0.587  U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (U0/I_NO_D.U_ILA/U_RST/HALT_pulse)
     LUT3:I0->O            1   0.068   0.417  U0/I_NO_D.U_ILA/U_RST/U_PRST1 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET1)
     LUT4:I3->O            8   0.068   0.445  U0/I_NO_D.U_ILA/U_RST/U_PRST0 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET0)
     FDS:S                     0.434          U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST
    ----------------------------------------
    Total                      2.394ns (0.945ns logic, 1.449ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================
Timing constraint: TS_J3_TO_D2 = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK" TIG;
  Clock period: 2.394ns (frequency: 417.711MHz)
  Total number of paths / destination ports: 1 / 1
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Delay:                  -2.606ns
  Source:               user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF)
  Destination:          user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
  Data Path Delay:      2.394ns (Levels of Logic = 2)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 0.000ns

  Data Path: user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF) to user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.375   0.587  U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (U0/I_NO_D.U_ILA/U_RST/HALT_pulse)
     LUT3:I0->O            1   0.068   0.417  U0/I_NO_D.U_ILA/U_RST/U_PRST1 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET1)
     LUT4:I3->O            8   0.068   0.445  U0/I_NO_D.U_ILA/U_RST/U_PRST0 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET0)
     FDS:S                     0.434          U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST
    ----------------------------------------
    Total                      2.394ns (0.945ns logic, 1.449ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================
Timing constraint: TS_J4_TO_D2 = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK" TIG;
  Clock period: 2.394ns (frequency: 417.711MHz)
  Total number of paths / destination ports: 1 / 1
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Delay:                  -2.606ns
  Source:               user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF)
  Destination:          user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
  Data Path Delay:      2.394ns (Levels of Logic = 2)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 0.000ns

  Data Path: user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF) to user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.375   0.587  U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (U0/I_NO_D.U_ILA/U_RST/HALT_pulse)
     LUT3:I0->O            1   0.068   0.417  U0/I_NO_D.U_ILA/U_RST/U_PRST1 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET1)
     LUT4:I3->O            8   0.068   0.445  U0/I_NO_D.U_ILA/U_RST/U_PRST0 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET0)
     FDS:S                     0.434          U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST
    ----------------------------------------
    Total                      2.394ns (0.945ns logic, 1.449ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================
Timing constraint: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 nS HIGH 15 nS
  Clock period: 1.753ns (frequency: 570.451MHz)
  Total number of paths / destination ports: 4056 / 488
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Slack:                  13.247ns
  Source:               user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR (FF)
  Data Path Delay:      1.753ns (Levels of Logic = 1)
  Source Clock:         user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT rising at 0.000ns
  Destination Clock:    user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL rising at 30.000ns

  Data Path: user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF) to user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.375   0.413  U0/U_ICON/U_iDATA_CMD (U0/U_ICON/iDATA_CMD)
     INV:I->O              8   0.086   0.445  U0/U_ICON/U_SYNC/U_iDATA_CMD_n (U0/U_ICON/U_SYNC/iDATA_CMD_n)
     FDR:R                     0.434          U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR
    ----------------------------------------
    Total                      1.753ns (0.895ns logic, 0.858ns route)
                                       (51.1% logic, 48.9% route)

=========================================================================
Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 nS
  Clock period: 1.753ns (frequency: 570.451MHz)
  Total number of paths / destination ports: 18 / 18
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Slack:                  13.247ns
  Source:               user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR (FF)
  Data Path Delay:      1.753ns (Levels of Logic = 1)
  Source Clock:         user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT rising at 0.000ns
  Destination Clock:    user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL rising at 15.000ns

  Data Path: user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF) to user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.375   0.413  U0/U_ICON/U_iDATA_CMD (U0/U_ICON/iDATA_CMD)
     INV:I->O              8   0.086   0.445  U0/U_ICON/U_SYNC/U_iDATA_CMD_n (U0/U_ICON/U_SYNC/iDATA_CMD_n)
     FDR:R                     0.434          U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR
    ----------------------------------------
    Total                      1.753ns (0.895ns logic, 0.858ns route)
                                       (51.1% logic, 48.9% route)

=========================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 nS
  Clock period: 1.284ns (frequency: 778.816MHz)
  Total number of paths / destination ports: 1 / 1
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Slack:                  13.716ns
  Source:               user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF)
  Data Path Delay:      1.284ns (Levels of Logic = 1)
  Source Clock:         user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT rising at 0.000ns
  Destination Clock:    user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT rising at 15.000ns

  Data Path: user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF) to user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/U_iDATA_CMD (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.375   0.413  U0/U_ICON/U_iDATA_CMD (U0/U_ICON/iDATA_CMD)
     INV:I->O              1   0.086   0.399  U0/U_ICON/U_iDATA_CMD_n (U0/U_ICON/iDATA_CMD_n)
     FDC:D                     0.011          U0/U_ICON/U_iDATA_CMD
    ----------------------------------------
    Total                      1.284ns (0.472ns logic, 0.812ns route)
                                       (36.8% logic, 63.2% route)

=========================================================================
Timing constraint: TS_J_TO_D = FROM TIMEGRP "J_CLK" TO TIMEGRP "D_CLK" TIG;
  Clock period: 2.394ns (frequency: 417.711MHz)
  Total number of paths / destination ports: 2417 / 341
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Delay:                  -2.606ns
  Source:               user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF)
  Destination:          user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
  Data Path Delay:      2.394ns (Levels of Logic = 2)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 0.000ns

  Data Path: user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF) to user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.375   0.587  U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (U0/I_NO_D.U_ILA/U_RST/HALT_pulse)
     LUT3:I0->O            1   0.068   0.417  U0/I_NO_D.U_ILA/U_RST/U_PRST1 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET1)
     LUT4:I3->O            8   0.068   0.445  U0/I_NO_D.U_ILA/U_RST/U_PRST0 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET0)
     FDS:S                     0.434          U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST
    ----------------------------------------
    Total                      2.394ns (0.945ns logic, 1.449ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================
Timing constraint: TS_D_TO_J = FROM TIMEGRP "D_CLK" TO TIMEGRP "J_CLK" TIG;
  Clock period: 2.394ns (frequency: 417.711MHz)
  Total number of paths / destination ports: 724 / 610
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Delay:                  -2.606ns
  Source:               user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF)
  Destination:          user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
  Data Path Delay:      2.394ns (Levels of Logic = 2)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 0.000ns

  Data Path: user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF) to user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.375   0.587  U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (U0/I_NO_D.U_ILA/U_RST/HALT_pulse)
     LUT3:I0->O            1   0.068   0.417  U0/I_NO_D.U_ILA/U_RST/U_PRST1 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET1)
     LUT4:I3->O            8   0.068   0.445  U0/I_NO_D.U_ILA/U_RST/U_PRST0 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET0)
     FDS:S                     0.434          U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST
    ----------------------------------------
    Total                      2.394ns (0.945ns logic, 1.449ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================
Timing constraint: TS_clk_5cc36873 = PERIOD TIMEGRP "clk_5cc36873" 5 nS HIGH 2.500 nS
  Clock period: 2.394ns (frequency: 417.711MHz)
  Total number of paths / destination ports: 2603 / 2296
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Slack:                  2.606ns
  Source:               user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF)
  Destination:          user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
  Data Path Delay:      2.394ns (Levels of Logic = 2)
  Source Clock:         to_register_clk rising at 0.000ns
  Destination Clock:    to_register_clk rising at 5.000ns

  Data Path: user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (FF) to user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.375   0.587  U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (U0/I_NO_D.U_ILA/U_RST/HALT_pulse)
     LUT3:I0->O            1   0.068   0.417  U0/I_NO_D.U_ILA/U_RST/U_PRST1 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET1)
     LUT4:I3->O            8   0.068   0.445  U0/I_NO_D.U_ILA/U_RST/U_PRST0 (U0/I_NO_D.U_ILA/U_RST/PRE_RESET0)
     FDS:S                     0.434          U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST
    ----------------------------------------
    Total                      2.394ns (0.945ns logic, 1.449ns route)
                                       (39.5% logic, 60.5% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock to_register_clk
-----------------------------------------------------------------------------+---------+---------+---------+---------+
                                                                             | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                                                                 |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------------------------------------------------------------------+---------+---------+---------+---------+
to_register_clk                                                              |    2.394|         |         |         |
user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL|    3.276|         |         |         |
-----------------------------------------------------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock user_logic_x0/chipscope/i_icon_for_syn/CONTROL0(13)
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
to_register_clk|         |         |    1.327|         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL
-----------------------------------------------------------------------------+---------+---------+---------+---------+
                                                                             | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                                                                 |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------------------------------------------------------------------+---------+---------+---------+---------+
to_register_clk                                                              |    2.842|         |         |         |
user_logic_x0/chipscope/i_icon_for_syn/CONTROL0(13)                          |         |    3.112|         |         |
user_logic_x0/chipscope/i_icon_for_syn/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL|    5.669|         |         |         |
user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT                        |    1.753|         |         |         |
-----------------------------------------------------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT
-----------------------------------------------------+---------+---------+---------+---------+
                                                     | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                                         |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------------------------------------------+---------+---------+---------+---------+
user_logic_x0/chipscope/i_icon_for_syn/U0/iUPDATE_OUT|    1.284|         |         |         |
-----------------------------------------------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 38.00 secs
Total CPU time to Xst completion: 37.28 secs
 
--> 

Total memory usage is 166760 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  498 (   0 filtered)
Number of infos    :  174 (   0 filtered)