Subversion Repositories pcie_sg_dma

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-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: O.76xd
--  \   \         Application: netgen
--  /   /         Filename: v6_bram4096x64.vhd
-- /___/   /\     Timestamp: Mon Mar 26 15:33:37 2012
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -w -sim -ofmt vhdl "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_bram4096x64.ngc" "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_bram4096x64.vhd" 
-- Device	: 6vlx240tff1156-1
-- Input file	: C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_bram4096x64.ngc
-- Output file	: C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_bram4096x64.vhd
-- # of Entities	: 1
-- Design Name	: v6_bram4096x64
-- Xilinx	: C:\Programmi\Xilinx\13.3\ISE_DS\ISE\
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity v6_bram4096x64 is
  port (
    clka : in STD_LOGIC := 'X'; 
    clkb : in STD_LOGIC := 'X'; 
    wea : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    web : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end v6_bram4096x64;
 
architecture STRUCTURE of v6_bram4096x64 is
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
 
begin
  XST_VCC : VCC
    port map (
      P => N0
    );
  XST_GND : GND
    port map (
      G => N1
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(63),
      DIADI(6) => dina(62),
      DIADI(5) => dina(61),
      DIADI(4) => dina(60),
      DIADI(3) => dina(59),
      DIADI(2) => dina(58),
      DIADI(1) => dina(57),
      DIADI(0) => dina(56),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(63),
      DIBDI(6) => dinb(62),
      DIBDI(5) => dinb(61),
      DIBDI(4) => dinb(60),
      DIBDI(3) => dinb(59),
      DIBDI(2) => dinb(58),
      DIBDI(1) => dinb(57),
      DIBDI(0) => dinb(56),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(63),
      DOADO(6) => douta(62),
      DOADO(5) => douta(61),
      DOADO(4) => douta(60),
      DOADO(3) => douta(59),
      DOADO(2) => douta(58),
      DOADO(1) => douta(57),
      DOADO(0) => douta(56),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(63),
      DOBDO(6) => doutb(62),
      DOBDO(5) => doutb(61),
      DOBDO(4) => doutb(60),
      DOBDO(3) => doutb(59),
      DOBDO(2) => doutb(58),
      DOBDO(1) => doutb(57),
      DOBDO(0) => doutb(56),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(7),
      WEA(2) => wea(7),
      WEA(1) => wea(7),
      WEA(0) => wea(7),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(7),
      WEBWE(2) => web(7),
      WEBWE(1) => web(7),
      WEBWE(0) => web(7)
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(55),
      DIADI(6) => dina(54),
      DIADI(5) => dina(53),
      DIADI(4) => dina(52),
      DIADI(3) => dina(51),
      DIADI(2) => dina(50),
      DIADI(1) => dina(49),
      DIADI(0) => dina(48),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(55),
      DIBDI(6) => dinb(54),
      DIBDI(5) => dinb(53),
      DIBDI(4) => dinb(52),
      DIBDI(3) => dinb(51),
      DIBDI(2) => dinb(50),
      DIBDI(1) => dinb(49),
      DIBDI(0) => dinb(48),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(55),
      DOADO(6) => douta(54),
      DOADO(5) => douta(53),
      DOADO(4) => douta(52),
      DOADO(3) => douta(51),
      DOADO(2) => douta(50),
      DOADO(1) => douta(49),
      DOADO(0) => douta(48),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(55),
      DOBDO(6) => doutb(54),
      DOBDO(5) => doutb(53),
      DOBDO(4) => doutb(52),
      DOBDO(3) => doutb(51),
      DOBDO(2) => doutb(50),
      DOBDO(1) => doutb(49),
      DOBDO(0) => doutb(48),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(6),
      WEA(2) => wea(6),
      WEA(1) => wea(6),
      WEA(0) => wea(6),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(6),
      WEBWE(2) => web(6),
      WEBWE(1) => web(6),
      WEBWE(0) => web(6)
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(47),
      DIADI(6) => dina(46),
      DIADI(5) => dina(45),
      DIADI(4) => dina(44),
      DIADI(3) => dina(43),
      DIADI(2) => dina(42),
      DIADI(1) => dina(41),
      DIADI(0) => dina(40),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(47),
      DIBDI(6) => dinb(46),
      DIBDI(5) => dinb(45),
      DIBDI(4) => dinb(44),
      DIBDI(3) => dinb(43),
      DIBDI(2) => dinb(42),
      DIBDI(1) => dinb(41),
      DIBDI(0) => dinb(40),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(47),
      DOADO(6) => douta(46),
      DOADO(5) => douta(45),
      DOADO(4) => douta(44),
      DOADO(3) => douta(43),
      DOADO(2) => douta(42),
      DOADO(1) => douta(41),
      DOADO(0) => douta(40),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(47),
      DOBDO(6) => doutb(46),
      DOBDO(5) => doutb(45),
      DOBDO(4) => doutb(44),
      DOBDO(3) => doutb(43),
      DOBDO(2) => doutb(42),
      DOBDO(1) => doutb(41),
      DOBDO(0) => doutb(40),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(5),
      WEA(2) => wea(5),
      WEA(1) => wea(5),
      WEA(0) => wea(5),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(5),
      WEBWE(2) => web(5),
      WEBWE(1) => web(5),
      WEBWE(0) => web(5)
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(39),
      DIADI(6) => dina(38),
      DIADI(5) => dina(37),
      DIADI(4) => dina(36),
      DIADI(3) => dina(35),
      DIADI(2) => dina(34),
      DIADI(1) => dina(33),
      DIADI(0) => dina(32),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(39),
      DIBDI(6) => dinb(38),
      DIBDI(5) => dinb(37),
      DIBDI(4) => dinb(36),
      DIBDI(3) => dinb(35),
      DIBDI(2) => dinb(34),
      DIBDI(1) => dinb(33),
      DIBDI(0) => dinb(32),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(39),
      DOADO(6) => douta(38),
      DOADO(5) => douta(37),
      DOADO(4) => douta(36),
      DOADO(3) => douta(35),
      DOADO(2) => douta(34),
      DOADO(1) => douta(33),
      DOADO(0) => douta(32),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(39),
      DOBDO(6) => doutb(38),
      DOBDO(5) => doutb(37),
      DOBDO(4) => doutb(36),
      DOBDO(3) => doutb(35),
      DOBDO(2) => doutb(34),
      DOBDO(1) => doutb(33),
      DOBDO(0) => doutb(32),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(4),
      WEA(2) => wea(4),
      WEA(1) => wea(4),
      WEA(0) => wea(4),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(4),
      WEBWE(2) => web(4),
      WEBWE(1) => web(4),
      WEBWE(0) => web(4)
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(31),
      DIADI(6) => dina(30),
      DIADI(5) => dina(29),
      DIADI(4) => dina(28),
      DIADI(3) => dina(27),
      DIADI(2) => dina(26),
      DIADI(1) => dina(25),
      DIADI(0) => dina(24),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(31),
      DIBDI(6) => dinb(30),
      DIBDI(5) => dinb(29),
      DIBDI(4) => dinb(28),
      DIBDI(3) => dinb(27),
      DIBDI(2) => dinb(26),
      DIBDI(1) => dinb(25),
      DIBDI(0) => dinb(24),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(31),
      DOADO(6) => douta(30),
      DOADO(5) => douta(29),
      DOADO(4) => douta(28),
      DOADO(3) => douta(27),
      DOADO(2) => douta(26),
      DOADO(1) => douta(25),
      DOADO(0) => douta(24),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(31),
      DOBDO(6) => doutb(30),
      DOBDO(5) => doutb(29),
      DOBDO(4) => doutb(28),
      DOBDO(3) => doutb(27),
      DOBDO(2) => doutb(26),
      DOBDO(1) => doutb(25),
      DOBDO(0) => doutb(24),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(3),
      WEA(2) => wea(3),
      WEA(1) => wea(3),
      WEA(0) => wea(3),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(3),
      WEBWE(2) => web(3),
      WEBWE(1) => web(3),
      WEBWE(0) => web(3)
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(23),
      DIADI(6) => dina(22),
      DIADI(5) => dina(21),
      DIADI(4) => dina(20),
      DIADI(3) => dina(19),
      DIADI(2) => dina(18),
      DIADI(1) => dina(17),
      DIADI(0) => dina(16),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(23),
      DIBDI(6) => dinb(22),
      DIBDI(5) => dinb(21),
      DIBDI(4) => dinb(20),
      DIBDI(3) => dinb(19),
      DIBDI(2) => dinb(18),
      DIBDI(1) => dinb(17),
      DIBDI(0) => dinb(16),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(23),
      DOADO(6) => douta(22),
      DOADO(5) => douta(21),
      DOADO(4) => douta(20),
      DOADO(3) => douta(19),
      DOADO(2) => douta(18),
      DOADO(1) => douta(17),
      DOADO(0) => douta(16),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(23),
      DOBDO(6) => doutb(22),
      DOBDO(5) => doutb(21),
      DOBDO(4) => doutb(20),
      DOBDO(3) => doutb(19),
      DOBDO(2) => doutb(18),
      DOBDO(1) => doutb(17),
      DOBDO(0) => doutb(16),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(2),
      WEA(2) => wea(2),
      WEA(1) => wea(2),
      WEA(0) => wea(2),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(2),
      WEBWE(2) => web(2),
      WEBWE(1) => web(2),
      WEBWE(0) => web(2)
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(15),
      DIADI(6) => dina(14),
      DIADI(5) => dina(13),
      DIADI(4) => dina(12),
      DIADI(3) => dina(11),
      DIADI(2) => dina(10),
      DIADI(1) => dina(9),
      DIADI(0) => dina(8),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(15),
      DIBDI(6) => dinb(14),
      DIBDI(5) => dinb(13),
      DIBDI(4) => dinb(12),
      DIBDI(3) => dinb(11),
      DIBDI(2) => dinb(10),
      DIBDI(1) => dinb(9),
      DIBDI(0) => dinb(8),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(15),
      DOADO(6) => douta(14),
      DOADO(5) => douta(13),
      DOADO(4) => douta(12),
      DOADO(3) => douta(11),
      DOADO(2) => douta(10),
      DOADO(1) => douta(9),
      DOADO(0) => douta(8),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(15),
      DOBDO(6) => doutb(14),
      DOBDO(5) => doutb(13),
      DOBDO(4) => doutb(12),
      DOBDO(3) => doutb(11),
      DOBDO(2) => doutb(10),
      DOBDO(1) => doutb(9),
      DOBDO(0) => doutb(8),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(1),
      WEA(2) => wea(1),
      WEA(1) => wea(1),
      WEA(0) => wea(1),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(1),
      WEBWE(2) => web(1),
      WEBWE(1) => web(1),
      WEBWE(0) => web(1)
    );
  U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_WRITE => FALSE,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "VIRTEX6",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9
    )
    port map (
      CASCADEINA => N1,
      CASCADEINB => N1,
      CASCADEOUTA => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED,
      CLKARDCLK => clka,
      CLKBWRCLK => clkb,
      DBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED,
      ENARDEN => N0,
      ENBWREN => N0,
      INJECTDBITERR => N1,
      INJECTSBITERR => N1,
      REGCEAREGCE => N1,
      REGCEB => N0,
      RSTRAMARSTRAM => N1,
      RSTRAMB => N1,
      RSTREGARSTREG => N1,
      RSTREGB => N1,
      SBITERR => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED,
      ADDRARDADDR(15) => N0,
      ADDRARDADDR(14) => addra(11),
      ADDRARDADDR(13) => addra(10),
      ADDRARDADDR(12) => addra(9),
      ADDRARDADDR(11) => addra(8),
      ADDRARDADDR(10) => addra(7),
      ADDRARDADDR(9) => addra(6),
      ADDRARDADDR(8) => addra(5),
      ADDRARDADDR(7) => addra(4),
      ADDRARDADDR(6) => addra(3),
      ADDRARDADDR(5) => addra(2),
      ADDRARDADDR(4) => addra(1),
      ADDRARDADDR(3) => addra(0),
      ADDRARDADDR(2) => N1,
      ADDRARDADDR(1) => N1,
      ADDRARDADDR(0) => N1,
      ADDRBWRADDR(15) => N0,
      ADDRBWRADDR(14) => addrb(11),
      ADDRBWRADDR(13) => addrb(10),
      ADDRBWRADDR(12) => addrb(9),
      ADDRBWRADDR(11) => addrb(8),
      ADDRBWRADDR(10) => addrb(7),
      ADDRBWRADDR(9) => addrb(6),
      ADDRBWRADDR(8) => addrb(5),
      ADDRBWRADDR(7) => addrb(4),
      ADDRBWRADDR(6) => addrb(3),
      ADDRBWRADDR(5) => addrb(2),
      ADDRBWRADDR(4) => addrb(1),
      ADDRBWRADDR(3) => addrb(0),
      ADDRBWRADDR(2) => N1,
      ADDRBWRADDR(1) => N1,
      ADDRBWRADDR(0) => N1,
      DIADI(31) => N1,
      DIADI(30) => N1,
      DIADI(29) => N1,
      DIADI(28) => N1,
      DIADI(27) => N1,
      DIADI(26) => N1,
      DIADI(25) => N1,
      DIADI(24) => N1,
      DIADI(23) => N1,
      DIADI(22) => N1,
      DIADI(21) => N1,
      DIADI(20) => N1,
      DIADI(19) => N1,
      DIADI(18) => N1,
      DIADI(17) => N1,
      DIADI(16) => N1,
      DIADI(15) => N1,
      DIADI(14) => N1,
      DIADI(13) => N1,
      DIADI(12) => N1,
      DIADI(11) => N1,
      DIADI(10) => N1,
      DIADI(9) => N1,
      DIADI(8) => N1,
      DIADI(7) => dina(7),
      DIADI(6) => dina(6),
      DIADI(5) => dina(5),
      DIADI(4) => dina(4),
      DIADI(3) => dina(3),
      DIADI(2) => dina(2),
      DIADI(1) => dina(1),
      DIADI(0) => dina(0),
      DIBDI(31) => N1,
      DIBDI(30) => N1,
      DIBDI(29) => N1,
      DIBDI(28) => N1,
      DIBDI(27) => N1,
      DIBDI(26) => N1,
      DIBDI(25) => N1,
      DIBDI(24) => N1,
      DIBDI(23) => N1,
      DIBDI(22) => N1,
      DIBDI(21) => N1,
      DIBDI(20) => N1,
      DIBDI(19) => N1,
      DIBDI(18) => N1,
      DIBDI(17) => N1,
      DIBDI(16) => N1,
      DIBDI(15) => N1,
      DIBDI(14) => N1,
      DIBDI(13) => N1,
      DIBDI(12) => N1,
      DIBDI(11) => N1,
      DIBDI(10) => N1,
      DIBDI(9) => N1,
      DIBDI(8) => N1,
      DIBDI(7) => dinb(7),
      DIBDI(6) => dinb(6),
      DIBDI(5) => dinb(5),
      DIBDI(4) => dinb(4),
      DIBDI(3) => dinb(3),
      DIBDI(2) => dinb(2),
      DIBDI(1) => dinb(1),
      DIBDI(0) => dinb(0),
      DIPADIP(3) => N1,
      DIPADIP(2) => N1,
      DIPADIP(1) => N1,
      DIPADIP(0) => N1,
      DIPBDIP(3) => N1,
      DIPBDIP(2) => N1,
      DIPBDIP(1) => N1,
      DIPBDIP(0) => N1,
      DOADO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED,
      DOADO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED,
      DOADO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED,
      DOADO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED,
      DOADO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED,
      DOADO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED,
      DOADO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED,
      DOADO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED,
      DOADO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED,
      DOADO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED,
      DOADO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED,
      DOADO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED,
      DOADO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED,
      DOADO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED,
      DOADO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED,
      DOADO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED,
      DOADO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED,
      DOADO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED,
      DOADO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED,
      DOADO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED,
      DOADO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED,
      DOADO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED,
      DOADO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED,
      DOADO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED,
      DOADO(7) => douta(7),
      DOADO(6) => douta(6),
      DOADO(5) => douta(5),
      DOADO(4) => douta(4),
      DOADO(3) => douta(3),
      DOADO(2) => douta(2),
      DOADO(1) => douta(1),
      DOADO(0) => douta(0),
      DOBDO(31) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED,
      DOBDO(30) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED,
      DOBDO(29) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED,
      DOBDO(28) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED,
      DOBDO(27) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED,
      DOBDO(26) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED,
      DOBDO(25) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED,
      DOBDO(24) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED,
      DOBDO(23) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED,
      DOBDO(22) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED,
      DOBDO(21) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED,
      DOBDO(20) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED,
      DOBDO(19) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED,
      DOBDO(18) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED,
      DOBDO(17) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED,
      DOBDO(16) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED,
      DOBDO(15) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED,
      DOBDO(14) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED,
      DOBDO(13) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED,
      DOBDO(12) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED,
      DOBDO(11) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED,
      DOBDO(10) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED,
      DOBDO(9) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED,
      DOBDO(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED,
      DOBDO(7) => doutb(7),
      DOBDO(6) => doutb(6),
      DOBDO(5) => doutb(5),
      DOBDO(4) => doutb(4),
      DOBDO(3) => doutb(3),
      DOBDO(2) => doutb(2),
      DOBDO(1) => doutb(1),
      DOBDO(0) => doutb(0),
      DOPADOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED,
      DOPADOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED,
      DOPADOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED,
      DOPADOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED,
      DOPBDOP(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED,
      DOPBDOP(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED,
      DOPBDOP(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED,
      DOPBDOP(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED,
      ECCPARITY(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED,
      RDADDRECC(8) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED,
      RDADDRECC(7) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED,
      RDADDRECC(6) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED,
      RDADDRECC(5) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED,
      RDADDRECC(4) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED,
      RDADDRECC(3) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED,
      RDADDRECC(2) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED,
      RDADDRECC(1) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED,
      RDADDRECC(0) => 
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED,
      WEA(3) => wea(0),
      WEA(2) => wea(0),
      WEA(1) => wea(0),
      WEA(0) => wea(0),
      WEBWE(7) => N1,
      WEBWE(6) => N1,
      WEBWE(5) => N1,
      WEBWE(4) => N1,
      WEBWE(3) => web(0),
      WEBWE(2) => web(0),
      WEBWE(1) => web(0),
      WEBWE(0) => web(0)
    );
 
end STRUCTURE;
 
-- synthesis translate_on