Subversion Repositories pcie_sg_dma

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-- Project    : Virtex-6 Integrated Block for PCI Express
-- File       : sys_clk_gen.vhd
-- Version    : 1.7
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity sys_clk_gen is
 
generic (
 
  CLK_FREQ : INTEGER := 250
 
);
 
port (
 
  sys_clk    : out std_logic
 
);
 
end sys_clk_gen;
 
 
architecture rtl of sys_clk_gen is
 
constant freq         : integer := CLK_FREQ; 
constant halfcycle    : TIME := 1 us/(2*freq);
signal sys_clk_c      : std_logic := '0';
 
begin
 
  sys_clk       <= sys_clk_c;
  sys_clk_c     <= not sys_clk_c after halfcycle;
 
end; -- sys_clk_gen