Subversion Repositories plb2wbbridge

BEGIN plb2wb_bridge

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = Bus and Bridge:MICROBLAZE
OPTION DESC = Plb-to-wishbone bridge


## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE

BUS_INTERFACE BUS = MWB, BUS_STD = WB, BUS_TYPE = MASTER


PARAMETER SYNCHRONY = true, DT = boolean, VALUES = ( true = synchron, false = asynchron )


## Parameters for WB
PARAMETER WB_DAT_W = 32,               DT = INTEGER,           ASSIGNMENT = CONSTANT
PARAMETER WB_ADR_W = 32,               DT = INTEGER,           ASSIGNMENT = CONSTANT
PARAMETER WB_ADR_OFFSET = 0x00000000,  DT = std_logic_vector
PARAMETER WB_ADR_OFFSET_NEG = 0,       DT = std_logic,         VALUES = ( 0 = false, 1 = true )
PARAMETER WB_PIC_INTS = 1,             DT = INTEGER,           RANGE = (1 : 32), 
PARAMETER WB_PIC_INT_LEVEL = 1,        DT = std_logic,         VALUES = ( 0 = active_low, 1 = active_high )
PARAMETER WB_TIMEOUT_CYCLES = 10,      DT = integer,           RANGE = (2 : 256 )
PARAMETER WB_SUPPORT_BLOCK = 1,        DT = integer,           VALUES = ( 1 = supported, 0 = not supported )


## Parameters for PLB
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB

PARAMETER C_STATUS_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_STATUS_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_STATUS_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_STATUS_BASEADDR, ADDRESS = HIGH, BUS = SPLB


PARAMETER C_SPLB_AWIDTH          = 32,    DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH          = 128,   DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS     = 8,     DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH       = 3,     DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH   = 32,    DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128),   ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SUPPORT_BUR_LINE= 1,     DT = INTEGER, BUS = SPLB, VALUES = ( 1 = supported, 0 = not supported )
PARAMETER C_SPLB_SUPPORT_ADR_PIPE= 1,     DT = INTEGER, BUS = SPLB, VALUES = ( 1 = supported, 0 = not supported )

## Ports PLB
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT PLB2WB_IRQ = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = MEDIUM
## Ports WB

 
PORT wb_clk_i    = "",        DIR = I,    SIGIS = CLK
PORT wb_rst_i    = "",        DIR = I,    SIGIS = RST
PORT wb_pic_int_i= "",        DIR = I,    VEC = [ WB_PIC_INTS-1: 0 ], SIGIS = INTERRUPT
PORT wb_dat_i = wb_m_dat_o,   DIR = IN ,  VEC = [ WB_DAT_W-1   : 0 ], BUS = MWB
PORT wb_dat_o = wb_m_dat_i,   DIR = OUT,  VEC = [ WB_DAT_W-1   : 0 ], BUS = MWB
PORT wb_adr_o = wb_m_adr_i,   DIR = OUT,  VEC = [ WB_ADR_W-1   : 0 ], BUS = MWB
PORT wb_sel_o = wb_m_sel_i,   DIR = OUT,  VEC = [ WB_DAT_W/8-1 : 0 ], BUS = MWB
PORT wb_we_o  = wb_m_we_i ,   DIR = OUT,  BUS = MWB
PORT wb_cyc_o = wb_m_cyc_i,   DIR = OUT,  BUS = MWB
PORT wb_stb_o = wb_m_stb_i,   DIR = OUT,  BUS = MWB
PORT wb_ack_i = wb_m_ack_o,   DIR = IN ,  BUS = MWB
PORT wb_err_i = wb_m_err_o,   DIR = IN ,  BUS = MWB
PORT wb_rty_i = wb_m_rty_o,   DIR = IN ,  BUS = MWB

# note: wb_lock_o is not used, because the arbiter doesn't support it.
# if u want to use a WB with wb_lock, use the following line      --,
#PORT wb_lock_o = "wb_m_lock_i",  DIR = OUT,  BUS = MWB         <---'
PORT wb_lock_o = "",          DIR = OUT,


END