Subversion Repositories plb2wbbridge

BEGIN testram

OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = Memory and Memory Controller:MICROBLAZE
OPTION DESC = Test-RAM

BUS_INTERFACE BUS = SWB, BUS_STD = WB, BUS_TYPE = SLAVE



PARAMETER MEM_FILE_NAME = "onchip_ram.bin", DT = STRING
PARAMETER WB_ADR_W      = 32, DT = INTEGER, BUS=SWB, ASSIGNMENT=CONSTANT
PARAMETER WB_DAT_W      = 32, DT = INTEGER, BIS=SWB, ASSIGNMENT=CONSTANT
PARAMETER RAM_ADR_W     = 15, DT = INTEGER
PARAMETER RD_DELAY      = 1,  DT = INTEGER
PARAMETER WR_DELAY      = 1,  DT = INTEGER

PARAMETER WITH_ERR_OR_RTY = 0b00, VALUES=( 0b00=none, 0b01=err, 0b10=rty, 0b11=none), DT = STD_LOGIC_VECTOR
PARAMETER ERR_RTY_INTERVAL = 0, DT = INTEGER

PORT wb_clk_i = "",          DIR = I, SIGIS = CLK
PORT wb_rst_i = "",          DIR = I, SIGIS = RST
PORT wb_adr_i = wb_s_adr_o,  DIR = I, VEC = [ WB_ADR_W-1 : 0 ],   BUS = SWB
PORT wb_stb_i = wb_s_stb_o,  DIR = I, BUS = SWB
PORT wb_cyc_i = wb_s_cyc_o,  DIR = I, BUS = SWB
PORT wb_we_i  = wb_s_we_o,   DIR = I, BUS = SWB
PORT wb_sel_i = wb_s_sel_o,  DIR = I, VEC = [ WB_DAT_W/8-1  : 0 ],   BUS = SWB
PORT wb_dat_i = wb_s_dat_o,  DIR = I, VEC = [ WB_DAT_W-1    : 0 ],   BUS = SWB
PORT wb_dat_o = wb_s_dat_i,  DIR = O, VEC = [ WB_DAT_W-1    : 0 ],   BUS = SWB
PORT wb_ack_o = wb_s_ack_i,  DIR = O, BUS = SWB
PORT wb_err_o = wb_s_err_i,  DIR = O, BUS = SWB
PORT wb_rty_o = wb_s_rty_i,  DIR = O, BUS = SWB