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BEGIN wb_conbus



OPTION IPTYPE = BUS
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION BUS_STD = WB
OPTION RUN_NGCBUILD = TRUE
OPTION MAX_MASTERS = 8
OPTION MAX_SLAVES = 8
OPTION DESC = Wishbone (WB) bus and arbiter
OPTION LONG_DESC = Wishbone (WB) bus and arbiter: Downloaded from: http://opencores.org/project,wb_conbus. Copyright (C) 2000 Authors and OPENCORES.ORG. You should have received a copy of the GNU Lesser General Public License along with this source; if not, download it from http://www.opencores.org/lgpl.shtml 
OPTION IP_GROUP = Bus and Bridge:MICROBLAZE
OPTION STYLE = HDL
OPTION TOP = wb_conbus_wrapper



PARAMETER WB_DAT_W         = 32, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER WB_ADR_W         = 32, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER wb_num_masters   = 8,  DT = integer, ASSIGNMENT = CONSTANT
PARAMETER wb_num_slaves    = 8,  DT = integer, ASSIGNMENT = CONSTANT

PARAMETER wb_s0_addr_w     = 4,     DT = integer, RANGE = ( 1 : 32 )
PARAMETER wb_s0_addr       = 0x0,   DT = std_logic_vector
PARAMETER wb_s1_addr_w     = 4,     DT = integer, RANGE = ( 1 : 32 )
PARAMETER wb_s1_addr       = 0x1,   DT = std_logic_vector
PARAMETER wb_s27_addr_w    = 8,     DT = integer, RANGE = ( 1 : 32 )
PARAMETER wb_s2_addr       = 0x92,  DT = std_logic_vector
PARAMETER wb_s3_addr       = 0x93,  DT = std_logic_vector
PARAMETER wb_s4_addr       = 0x94,  DT = std_logic_vector
PARAMETER wb_s5_addr       = 0x95,  DT = std_logic_vector
PARAMETER wb_s6_addr       = 0x96,  DT = std_logic_vector
PARAMETER wb_s7_addr       = 0x97,  DT = std_logic_vector


PORT     wb_clk_i    = "",          DIR = I, SIGIS = CLK
PORT     wb_rst_i    = "",          DIR = I, SIGIS = RST
PORT     wb_m_dat_i  = wb_m_dat_i,  DIR = I, VEC = [ (WB_DAT_W*wb_num_masters)-1    : 0 ]
PORT     wb_m_dat_o  = wb_m_dat_o,  DIR = O, VEC = [ WB_DAT_W-1                     : 0 ]
PORT     wb_m_adr_i  = wb_m_adr_i,  DIR = I, VEC = [ (WB_ADR_W*wb_num_masters)-1    : 0 ]
PORT     wb_m_sel_i  = wb_m_sel_i,  DIR = I, VEC = [ (WB_DAT_W/8*wb_num_masters)-1  : 0 ] 
PORT     wb_m_we_i   = wb_m_we_i,   DIR = I, VEC = [ wb_num_masters-1               : 0 ] 
PORT     wb_m_cyc_i  = wb_m_cyc_i,  DIR = I, VEC = [ wb_num_masters-1               : 0 ]
PORT     wb_m_stb_i  = wb_m_stb_i,  DIR = I, VEC = [ wb_num_masters-1               : 0 ]
PORT     wb_m_ack_o  = wb_m_ack_o,  DIR = O, VEC = [ wb_num_masters-1               : 0 ]
PORT     wb_m_err_o  = wb_m_err_o,  DIR = O, VEC = [ wb_num_masters-1               : 0 ]
PORT     wb_m_rty_o  = wb_m_rty_o,  DIR = O, VEC = [ wb_num_masters-1               : 0 ]
PORT     wb_m_cab_i  = wb_m_cab_i,  DIR = I, VEC = [ wb_num_masters-1               : 0 ]
                      
PORT     wb_s_dat_i  = wb_s_dat_i,  DIR = I, VEC = [WB_DAT_W*wb_num_slaves-1        : 0 ] 
PORT     wb_s_dat_o  = wb_s_dat_o,  DIR = O, VEC = [WB_DAT_W-1                      : 0 ]
PORT     wb_s_adr_o  = wb_s_adr_o,  DIR = O, VEC = [WB_ADR_W-1                      : 0 ]
PORT     wb_s_sel_o  = wb_s_sel_o,  DIR = O, VEC = [WB_DAT_W/8-1                    : 0 ]
PORT     wb_s_we_o   = wb_s_we_o,   DIR = O,                                      
PORT     wb_s_cyc_o  = wb_s_cyc_o,  DIR = O,                                      
PORT     wb_s_stb_o  = wb_s_stb_o,  DIR = O, VEC = [wb_num_slaves-1                 : 0 ]
PORT     wb_s_ack_i  = wb_s_ack_i,  DIR = I, VEC = [wb_num_slaves-1                 : 0 ]
PORT     wb_s_err_i  = wb_s_err_i,  DIR = I, VEC = [wb_num_slaves-1                 : 0 ]
PORT     wb_s_rty_i  = wb_s_rty_i,  DIR = I, VEC = [wb_num_slaves-1                 : 0 ]
PORT     wb_s_cab_o  = wb_s_cab_o,  DIR = O


END