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[/] [pulse_processing_algorithm/] [FeatureExtraction.vhd] - Rev 2
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----------------------------------------------------------------------------------------------- -- -- Copyright (C) 2011 Peter Lemmens, PANDA collaboration -- p.j.j.lemmens@rug.nl -- http://www-panda.gsi.de -- -- As a reference, please use: -- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner, -- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter" -- Nuclear Inst. and Methods in Physics Research, A .... -- -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA -- ----------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------- -- Company: KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands -- Author: P.J.J. Lemmens -- Design Name: Feature Extraction -- Module Name: Feature_Extraction -- Description: - VME interface for SIS3302 by Struck, modified by KVI -- - 2 channels Feature-extraction ----------------------------------------------------------------------------------------------- -- Generics : -- Parameters : ----------------------------------------------------------------------------------------------- library IEEE; USE ieee.std_logic_1164.all ; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; entity Feature_Extraction is port( uP_CLK : in std_logic; Reset : in std_logic; ADC_CLK : in std_logic; ADCin : in std_logic_vector(15 downto 0); invert_data_in : in std_logic; externaltrigger : in std_logic; softwaretrigger : in std_logic; cmd_output_select : in std_logic_vector(3 downto 0); cmd_start_adc : in std_logic; cmd_enableFE : in std_logic; cmd_baseline_enable : in std_logic; cmd_double_CF : in std_logic; cmd_program_params : in std_logic; cmd_bypass_mwd : in std_logic; cmd_bypass_reshape : in std_logic; decay_correction_in : in STD_LOGIC_VECTOR(31 downto 0); reshape_correction_in : in STD_LOGIC_VECTOR(31 downto 0); buffer_size : in std_logic_vector(31 downto 0); -- number of samples to read from buffer int_signal_threshold_in : in std_logic_vector(15 downto 0); -- event-trigger threshold on the integrated input signal mwd_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for mwd size cf_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for cf delay cf_integral_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for cf-generation baseline_pwr_in : in STD_LOGIC_VECTOR(7 downto 0); baseline_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- baseline data-collect inhibition after event event_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- event detect inhibition after event fb_flowctrl_running : out std_logic; fb_chain_enable : out std_logic; feedback_port0 : out std_logic_vector(31 downto 0); feedback_port1 : out std_logic_vector(31 downto 0); feedback_port2 : out std_logic_vector(15 downto 0); feedback_port3 : out std_logic_vector(31 downto 0); adc_ram_fifo_data_wr_data : out std_logic_vector(31 downto 0); adc_ram_fifo_address : out std_logic_vector(31 downto 0); adc_ram_fifo_data_wr_ce : out std_logic; adc_ram_fifo_addr_wr_ce : out std_logic; last_buffer_adc_ram_fifo_wr_addr : out std_logic_vector(31 downto 0) ); end Feature_Extraction; architecture behaviour of Feature_Extraction is constant WIDTH : natural := 16; -- width of data constant MAX_MWD_PWR : natural := 6; -- max. constant MAX_CF_PWR : natural := 5; -- max. constant MAX_BASELINE_PWR : natural := 9; -- max. length of baseline averaging (2^10=1024) constant ZEROX_WINDOW_PWR : natural := 1; -- length of zero-crossing window (2^2=4 samples) constant ZEROX_THRESHOLD_PWR : natural := 0; -- magnitude of zero-crossing threshold (2^5=32) constant INTERP_CYCLES : natural := 11; -- interpolation cycles for time-fraction calculation constant FRACTION_SIZE : natural := INTERP_CYCLES;-- - ZEROX_WINDOW_PWR; --all interp bits are fraction now !! interp between 2 samples constant BASE_ADDR : std_logic_vector(31 downto 0) := (others => '0'); -- vme-mem base address for ringbuffer COMPONENT MWD_CF_process generic( WIDTH : natural := 1; MAX_MWD_PWR : natural := 1; MAX_CF_PWR : natural := 1; MAX_BASELINE_PWR : natural := 1; ZEROX_WINDOW_PWR : natural := 1; ZEROX_THRESHOLD_PWR : natural := 1; INTERP_CYCLES : natural := 1 ); Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; enable : in STD_LOGIC; program : in STD_LOGIC; baseline_enable : in STD_LOGIC; double_CF_in : in STD_LOGIC; bypass_mwd : in STD_LOGIC; bypass_reshape : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (WIDTH - 1 downto 0); invert_data_in : in STD_LOGIC; decay_correction_in : in STD_LOGIC_VECTOR; reshape_correction_in : in STD_LOGIC_VECTOR; threshold_in : in STD_LOGIC_VECTOR; mwd_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for mwd-windowsize cf_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for cf-delay cf_integral_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for CF integral baseline_pwr_in : in STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); baseline_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- baseline data-collect inhibition after event event_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- event detect inhibition after event mwd_switch_out : out STD_LOGIC_VECTOR; baseline_out : out STD_LOGIC_VECTOR; clamped_out : out STD_LOGIC_VECTOR; del_clamp_out : out STD_LOGIC_VECTOR; CFdev_clamp_out : out STD_LOGIC_VECTOR; cf_trace_out : out STD_LOGIC_VECTOR; integral : out STD_LOGIC_VECTOR; sample_nr : out STD_LOGIC_VECTOR; zeroX_out : out STD_LOGIC; event_detect_out : out STD_LOGIC; bl_gate_out : out STD_LOGIC; ed_gate_out : out STD_LOGIC; eventdata_valid : out STD_LOGIC; eventnr_out : out STD_LOGIC_VECTOR; fraction : out STD_LOGIC_VECTOR; energy : out STD_LOGIC_VECTOR ); END COMPONENT; COMPONENT output_mux Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; input_valid : in STD_LOGIC; energy_in : in STD_LOGIC_VECTOR; eventnr_in : in STD_LOGIC_VECTOR; fraction_in : in STD_LOGIC_VECTOR; output_valid : out STD_LOGIC; outdata16 : out STD_LOGIC_VECTOR(15 downto 0) ); end COMPONENT; component output_select PORT ( clk : in std_logic; output_select : in std_logic_vector; indata_in : in std_logic_vector; -- Feature Extraction data_in mwd_in : in std_logic_vector; baseline_in : in std_logic_vector; clamped_in : in std_logic_vector; del_clamp_in : in std_logic_vector; CFdev_clamp_in : in std_logic_vector; cf_trace_in : in std_logic_vector; integral_in : in std_logic_vector; zerox_in : in std_logic; eventdetect_in : in std_logic; gate_in : in std_logic; energy_in : in std_logic_vector; mux_data_in : in std_logic_vector; samplenr_in : in STD_LOGIC_VECTOR; fraction_in : in STD_LOGIC_VECTOR; mux_data_valid_in : in std_logic; fe_data_valid : in std_logic; dataword_out : out std_logic_vector; data_out_valid : out std_logic ); end component; component adc_flowcontrol port( rst : in std_logic; clk : in std_logic; program_in : in std_logic;-- data_available : in std_logic; start_adc : in std_logic; ext_trigger : in std_logic; soft_trigger : in std_logic; running : out std_logic; chain_enable : out std_logic; sync_init_out : out std_logic;-- sync_rst_out : out std_logic;-- rst_addr_gen_out : out std_logic; write_count : out std_logic_vector(15 downto 0) ); end component; component ringbuffer_feed port( rst : in std_logic; clk : in std_logic; enable : in std_logic; data_in : in std_logic_vector(15 downto 0); address_in : in std_logic_vector(31 downto 0); data_out_valid : out std_logic; addr_out_valid : out std_logic; data_out : out std_logic_vector(31 downto 0); address_out : out std_logic_vector(31 downto 0) ); end component; component ddr_address_generator port( clk : in std_logic; rst : in std_logic; enable : in std_logic; program : in std_logic; restart : in std_logic; base_address_in : in std_logic_vector; buffersize_in : in std_logic_vector; address_out : out std_logic_vector ); end component; component control_feedback port( rst : in std_logic; ADclk : in std_logic; uPclk : in std_logic; cmd_output_select : in std_logic_vector(3 downto 0); buffersize : in std_logic_vector(31 downto 0); chain_enable : in std_logic; flowctrl_running : in std_logic; output_select_valid : in std_logic; fb_output_select : out std_logic_vector(3 downto 0); fb_buffersize : out std_logic_vector(31 downto 0); fb_chain_enable : out std_logic; fb_running : out std_logic; fb_output_valid : out std_logic ); end component; component async_fifo_16x65 port (din : IN std_logic_VECTOR(64 downto 0); rd_clk : IN std_logic; rd_en : IN std_logic; rst : IN std_logic; wr_clk : IN std_logic; wr_en : IN std_logic; dout : OUT std_logic_VECTOR(64 downto 0); empty : OUT std_logic; full : OUT std_logic; valid : OUT std_logic ); end component; --type output_mode_type is (none,energytime,traces,both); ------------------------------------------------------------------------------------------------------ signal rst_S : std_logic := '1'; signal ADclk_S : std_logic := '0'; signal uPclk_S : std_logic := '0'; signal enable_S : std_logic := '0'; signal ADCin_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0'); signal s16out_ADCin_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0'); signal invert_data_in_S : std_logic := '0'; signal cmd_baseline_enable_S : std_logic := '0'; signal cmd_double_CF_S : std_logic := '0'; signal cmd_program_params_S : std_logic := '0'; signal cmd_bypass_mwd_S : std_logic := '0'; signal cmd_bypass_reshape_S : std_logic := '0'; signal FE_init_S : std_logic := '0'; signal FE_reset_S : std_logic := '0'; signal rst_addr_gen_S : std_logic := '0'; signal ext_trigger_S : std_logic := '0'; signal soft_trigger_S : std_logic := '0'; signal cmd_start_adc_S : std_logic := '0'; signal mwd_switch_out_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0'); signal baseline_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0'); signal clamped_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0'); signal del_clamp_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0'); signal CFdev_clamp_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0'); signal cf_trace_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0'); signal integral_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0'); signal samplenr_S : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); signal eventnr_S : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); signal fraction_S : STD_LOGIC_VECTOR(FRACTION_SIZE - 1 downto 0) := (others => '0'); signal energy_S : STD_LOGIC_VECTOR (WIDTH downto 0) := (others => '0'); signal mwd_out_S : std_logic_vector(WIDTH - 1 downto 0); signal baseline_out_S : std_logic_vector(WIDTH - 1 downto 0); signal clamped_out_S : std_logic_vector(WIDTH - 1 downto 0); signal del_clamp_out_S : std_logic_vector(WIDTH - 1 downto 0); signal CFdev_clamp_out_S : std_logic_vector(WIDTH - 1 downto 0); signal cf_trace_out_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0); signal integral_out_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0); signal energy_out_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0); signal zeroX_out_S : STD_LOGIC := '0'; signal event_detect_S : STD_LOGIC := '0'; signal bl_gate_out_S : STD_LOGIC := '0'; signal ed_gate_out_S : STD_LOGIC := '0'; signal eventdata_valid_S : STD_LOGIC := '0'; signal mux_out_valid_S : STD_LOGIC := '0'; signal mux_data_out_S : std_logic_vector(15 downto 0) := (others => '0'); signal cmd_output_select_S : std_logic_vector(3 downto 0) := (others => '0'); signal output_select_dout_S : std_logic_vector(15 downto 0) := (others => '0'); signal output_select_valid_S : std_logic := '0'; signal data_available_S : std_logic := '0'; signal flowctrl_running_S : std_logic := '0'; signal chain_enable_S : STD_LOGIC := '0'; signal data_dcplfifo_write_en_S : STD_LOGIC := '0'; signal addr_dcplfifo_write_en_S : STD_LOGIC := '0'; -- signal dcplfifo_write_en_S : STD_LOGIC := '0'; -- never used. data_dcplfifo_write_en_S is used instead as writes are done every (data)cycle signal dcplfifo_empty_S : STD_LOGIC := '0'; signal dcplfifo_read_S : STD_LOGIC := '0'; signal dcplfifo_valid_S : STD_LOGIC := '0'; signal decay_correction_S : std_logic_vector (decay_correction_in'high downto 0) := (others => '0'); signal reshape_correction_S : std_logic_vector (reshape_correction_in'high downto 0) := (others => '0'); signal buffersize_S : std_logic_vector(31 downto 0) := (others => '0'); signal address_gen_S : std_logic_vector(31 downto 0) := (others => '0'); signal int_signal_threshold_S : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); signal mwd_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(5, 8); -- original default value -- signal fb_window_size_S : std_logic_vector(7 downto 0); signal cf_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(4, 8); -- original default value signal cf_integral_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(4, 8); -- original default value = (mwd_power - 1) signal baseline_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal baseline_inhibit_cnt_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value signal event_inhibit_cnt_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(16, 8); -- original default value signal adc_ram_fifo_data_wr_ce_S : STD_LOGIC := '0'; -- signal adc_ram_fifo_addr_wr_ce_S : STD_LOGIC := '0'; -- not used. port is driven from async logic function signal feed2dcpl_fifo_data_S : std_logic_vector(31 downto 0) := (others => '0'); signal feed2dcpl_fifo_addr_S : std_logic_vector(31 downto 0) := (others => '0'); signal feed2dcpl_fifo_wide_S : std_logic_vector(64 downto 0) := (others => '0'); signal dcpl_fifo2rb_wide_S : std_logic_vector(64 downto 0) := (others => '0'); signal dcpl_fifo2rb_data_S : std_logic_vector(31 downto 0) := (others => '0'); signal dcpl_fifo2rb_addr_S : std_logic_vector(31 downto 0) := (others => '0'); signal dcpl_fifo2rb_state_S : std_logic := '0'; signal fb_output_select_S : std_logic_vector(3 downto 0) := (others => '0'); signal fb_buffersize_s : std_logic_vector(31 downto 0) := (others => '0'); signal fb_chain_enable_S : std_logic := '0'; signal fb_flowctrl_running_S : std_logic := '0'; signal fb_output_select_valid_S : std_logic := '0'; signal fb_write_count_S : std_logic_vector(15 downto 0) := (others => '0'); signal feedback_bus0_S : std_logic_vector(31 downto 0) := (others => '0'); signal feedback_bus1_S : std_logic_vector(31 downto 0) := (others => '0'); begin s16out_ADCin_S <= conv_std_logic_vector(conv_integer(unsigned(ADCin_S(15 downto 1))), WIDTH) when invert_data_in_S = '0' else conv_std_logic_vector(- conv_integer(unsigned(ADCin_S(15 downto 1))), WIDTH); FE_inst: MWD_CF_process generic map(WIDTH => WIDTH, MAX_MWD_PWR => MAX_MWD_PWR, MAX_CF_PWR => MAX_CF_PWR, MAX_BASELINE_PWR => MAX_BASELINE_PWR, ZEROX_WINDOW_PWR => ZEROX_WINDOW_PWR, ZEROX_THRESHOLD_PWR => ZEROX_THRESHOLD_PWR, INTERP_CYCLES => INTERP_CYCLES ) PORT MAP( rst => FE_reset_S, --rst_S, clk => ADclk_S, enable => enable_S, program => FE_init_S, baseline_enable => cmd_baseline_enable_S, double_CF_in => cmd_double_CF_S, bypass_mwd => cmd_bypass_mwd_S, bypass_reshape => cmd_bypass_reshape_S, data_in => ADCin_S, invert_data_in => invert_data_in_S, decay_correction_in => decay_correction_S, reshape_correction_in => reshape_correction_S, threshold_in => int_signal_threshold_S, mwd_pwr_in => mwd_pwr_S, cf_pwr_in => cf_pwr_s, cf_integral_pwr_in => cf_integral_pwr_s, baseline_pwr_in => baseline_pwr_S, baseline_inhibit_cnt_in => baseline_inhibit_cnt_S, event_inhibit_cnt_in => event_inhibit_cnt_S, mwd_switch_out => mwd_switch_out_S, baseline_out => baseline_S, clamped_out => clamped_S, del_clamp_out => del_clamp_S, CFdev_clamp_out => CFdev_clamp_S, cf_trace_out => cf_trace_S, integral => integral_S, sample_nr => samplenr_S, zeroX_out => zeroX_out_S, event_detect_out => event_detect_S, bl_gate_out => bl_gate_out_S, ed_gate_out => ed_gate_out_S, eventdata_valid => eventdata_valid_S, eventnr_out => eventnr_S, fraction => fraction_S, energy => energy_S ); data_mux : output_mux Port map(rst => FE_reset_S, --rst_S, clk => ADclk_S, input_valid => eventdata_valid_S, energy_in => energy_S, eventnr_in => eventnr_S, fraction_in => fraction_S, output_valid => mux_out_valid_S, outdata16 => mux_data_out_S ); data_select: output_select PORT MAP(clk => ADclk_S, output_select => cmd_output_select_S, indata_in => s16out_ADCin_S, mwd_in => mwd_out_S, baseline_in => baseline_out_S, clamped_in => clamped_out_S, del_clamp_in => del_clamp_out_S, CFdev_clamp_in => CFdev_clamp_out_S, cf_trace_in => cf_trace_out_S, integral_in => integral_out_S, zerox_in => zeroX_out_S, eventdetect_in => event_detect_S, gate_in => bl_gate_out_S, energy_in => energy_out_S, mux_data_in => mux_data_out_S, samplenr_in => samplenr_S, fraction_in => fraction_S, mux_data_valid_in => mux_out_valid_S, fe_data_valid => enable_S, dataword_out => output_select_dout_S, data_out_valid => output_select_valid_S ); ---------------------------------------------------------------------------------- -- STOMA ---------------------------------------------------------------------------------- last_buffer_adc_ram_fifo_wr_addr(15 downto 0) <= output_select_dout_S; ---------------------------------------------------------------------------------- FE_flow_control : adc_flowcontrol port map(rst => rst_S, clk => ADclk_S, program_in => cmd_program_params_S, data_available => data_available_S, start_adc => cmd_start_adc_S, ext_trigger => ext_trigger_S, soft_trigger => soft_trigger_S, running => flowctrl_running_S, chain_enable => chain_enable_S, sync_init_out => FE_init_S, sync_rst_out => FE_reset_S, rst_addr_gen_out => rst_addr_gen_S, write_count => fb_write_count_S ); FE_ringbuf_feed : ringbuffer_feed port map(rst => FE_reset_S, clk => ADclk_S, enable => chain_enable_S, data_in => output_select_dout_S, address_in => address_gen_S, data_out_valid => data_dcplfifo_write_en_S, -- !! addr_out_valid => addr_dcplfifo_write_en_S, --!! data_out => feed2dcpl_fifo_data_S, address_out => feed2dcpl_fifo_addr_S ); FE_vme_addr_gen: ddr_address_generator port map(clk => ADclk_S, rst => FE_reset_S, enable => chain_enable_S, program => FE_init_S, restart => rst_addr_gen_S, base_address_in => BASE_ADDR, buffersize_in => buffersize_S, address_out => address_gen_S ); FE_control_UI : control_feedback port map(rst => FE_reset_S, ADclk => ADclk_S, uPclk => uPclk_S, cmd_output_select => cmd_output_select, buffersize => buffersize_S, chain_enable => chain_enable_S, flowctrl_running => flowctrl_running_S, output_select_valid => output_select_valid_S, fb_output_select => fb_output_select_S, fb_buffersize => fb_buffersize_S, fb_chain_enable => fb_chain_enable_S, fb_running => fb_flowctrl_running_S, fb_output_valid => fb_output_select_valid_S ); adc2uP_fifo : async_fifo_16x65 -- clock domain decoupling buffer for VME/ringbufferdata port map(rst => FE_reset_S, rd_clk => uPclk_S, rd_en => dcplfifo_read_S, din => feed2dcpl_fifo_wide_S, wr_clk => ADclk_S, wr_en => data_dcplfifo_write_en_S, -- dout => dcpl_fifo2rb_wide_S, empty => dcplfifo_empty_S, full => open, valid => dcplfifo_valid_S ); --- connect the wires !!------------------------------------------------------------------------------ dcplfifo_read_S <= not dcplfifo_empty_S; feed2dcpl_fifo_wide_S(31 downto 0) <= feed2dcpl_fifo_data_S; feed2dcpl_fifo_wide_S(63 downto 32) <= feed2dcpl_fifo_addr_S; feed2dcpl_fifo_wide_S(64) <= addr_dcplfifo_write_en_S; dcpl_fifo2rb_data_S <= dcpl_fifo2rb_wide_S(31 downto 0); dcpl_fifo2rb_addr_S <= dcpl_fifo2rb_wide_S(63 downto 32); dcpl_fifo2rb_state_S <= dcpl_fifo2rb_wide_S(64); --- now sync the read/write process with wme clock--------------------- vme_interface_sync : process(uPclk_S) begin if rising_edge(uPclk_S) then adc_ram_fifo_data_wr_ce_S <= dcplfifo_read_S; --data_dcplfifo_read_S; if (dcplfifo_valid_S = '1') then adc_ram_fifo_data_wr_ce <= adc_ram_fifo_data_wr_ce_S; adc_ram_fifo_addr_wr_ce <= dcpl_fifo2rb_state_S and adc_ram_fifo_data_wr_ce_S; -- comes from fifo and is allready delayed 1 extra else adc_ram_fifo_data_wr_ce <= '0'; adc_ram_fifo_addr_wr_ce <= '0'; end if; adc_ram_fifo_data_wr_data <= dcpl_fifo2rb_data_S; adc_ram_fifo_address <= dcpl_fifo2rb_addr_S; end if; end process; ADclk_S <= ADC_CLK; uPclk_S <= uP_CLK; data_available_S <= output_select_valid_S; decay_correction_S <= decay_correction_in; reshape_correction_S <= reshape_correction_in; int_signal_threshold_S <= int_signal_threshold_in; mwd_pwr_S <= mwd_pwr_in; cf_pwr_s <= cf_pwr_in; cf_integral_pwr_s <= cf_integral_pwr_in; baseline_pwr_S <= baseline_pwr_in; baseline_inhibit_cnt_S <= baseline_inhibit_cnt_in; event_inhibit_cnt_S <= event_inhibit_cnt_in; fb_flowctrl_running <= flowctrl_running_S; fb_chain_enable <= fb_chain_enable_S; mwd_out_S(15 downto 0) <= mwd_switch_out_S(16 downto 1); integral_out_S (15 downto 0) <= integral_S(16 downto 1); energy_out_S(15 downto 0) <= energy_S(16 downto 1); del_clamp_out_S(15 downto 0) <= del_clamp_S(16 downto 1); clamped_out_S(15 downto 0) <= clamped_S(16 downto 1); cf_trace_out_S(15 downto 0) <= cf_trace_S(16 downto 1); baseline_out_S(15 downto 0) <= baseline_S(16 downto 1); CFdev_clamp_out_S(15 downto 0)<= CFdev_clamp_S(16 downto 1); feedback_bus0_S <= fb_buffersize_S; feedback_bus1_S(3 downto 0) <= fb_output_select_S; feedback_bus1_S(9 downto 4) <= (others => '0'); feedback_bus1_S(10) <= fb_chain_enable_S; feedback_bus1_S(11) <= fb_flowctrl_running_S; feedback_bus1_S(12) <= fb_output_select_valid_S; feedback_bus1_S(15 downto 13) <= (others => '0'); feedback_bus1_S(23 downto 16) <= (others => '0'); --fb_window_size_S; feedback_bus1_S(31 downto 24) <= cf_pwr_S; feedback_port0 <= feedback_bus0_S; feedback_port1 <= feedback_bus1_S; feedback_port2 <= fb_write_count_S; feedback_port3 <= dcpl_fifo2rb_addr_S; last_buffer_adc_ram_fifo_wr_addr(31 downto 16) <= (others => '0'); -- was not driven... to avoid warning 1305 -- data_dcplfifo_read_S <= not data_dcplfifo_empty_S; -- addr_dcplfifo_read_S <= not addr_dcplfifo_empty_S; ADC2vme_interface_sync : process(ADclk_S) begin if rising_edge(ADclk_S) then -- input sync rst_S <= Reset; ADCin_S <= ADCin; invert_data_in_S <= invert_data_in; ext_trigger_S <= externaltrigger; soft_trigger_S <= softwaretrigger; cmd_output_select_S <= cmd_output_select; cmd_start_adc_S <= cmd_start_adc; cmd_baseline_enable_S <= cmd_baseline_enable; cmd_double_CF_S <= cmd_double_CF; enable_S <= cmd_enableFE; cmd_program_params_S <= cmd_program_params; cmd_bypass_mwd_S <= cmd_bypass_mwd; cmd_bypass_reshape_S <= cmd_bypass_reshape; buffersize_S <= buffer_size; -- Aanpassen breedte van buffersize voor ddr_address_gen end if; end process; end behaviour;