Subversion Repositories pulse_processing_algorithm

-----------------------------------------------------------------------------------------------
--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company:			KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author:			P.J.J. Lemmens
-- Design Name:	Feature Extraction
-- Module Name:	MWD_CF_process.vhd
-- Description:	- Moving Window Deconvolution				("MWD_programmable")
--						- Pulse Reshape module						("shaper")
--						- switch/multiplexer							("mux_sre") 
--						- Constant Fraction pulse-detection		("CF_process")
-----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
 
entity MWD_CF_process is
	generic(	WIDTH							:	natural	:= 1;
				MAX_MWD_PWR					:	natural	:= 1;
				MAX_CF_PWR					:	natural	:=	1;
				MAX_BASELINE_PWR			:	natural	:=	1;
				ZEROX_WINDOW_PWR			:	natural	:=	1;
				ZEROX_THRESHOLD_PWR		:	natural	:=	1;
				INTERP_CYCLES				:	natural	:=	1
			);
	Port (	rst							: in STD_LOGIC;
				clk							: in STD_LOGIC;
				enable						: in STD_LOGIC;
				program						: in STD_LOGIC;
				baseline_enable			: in STD_LOGIC;
				double_CF_in				: in STD_LOGIC;
				bypass_mwd					: in STD_LOGIC;
				bypass_reshape				: in STD_LOGIC;
				data_in						: in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
				invert_data_in				: in STD_LOGIC;
				decay_correction_in		: in STD_LOGIC_VECTOR;
				reshape_correction_in	: in STD_LOGIC_VECTOR;
				threshold_in				: in STD_LOGIC_VECTOR;
				mwd_pwr_in					: in std_logic_vector(7 downto 0);  -- power of 2 for mwd-windowsize
				cf_pwr_in					: in std_logic_vector(7 downto 0);  -- power of 2 for cf-delay
				cf_integral_pwr_in		: in std_logic_vector(7 downto 0);  -- power of 2 for CF integral 
				baseline_pwr_in			: in	STD_LOGIC_VECTOR(7 downto 0);
				baseline_inhibit_cnt_in	: in std_logic_vector(7 downto 0);  -- baseline data-collect inhibition after event
				event_inhibit_cnt_in		: in std_logic_vector(7 downto 0);  -- event detect inhibition after event
				mwd_switch_out				: out STD_LOGIC_VECTOR;
				baseline_out				: out STD_LOGIC_VECTOR;
				clamped_out					: out STD_LOGIC_VECTOR;
				del_clamp_out				: out STD_LOGIC_VECTOR;
				CFdev_clamp_out			: out STD_LOGIC_VECTOR;
				cf_trace_out				: out STD_LOGIC_VECTOR;
				integral						: out STD_LOGIC_VECTOR;
				sample_nr					: out STD_LOGIC_VECTOR;
				zeroX_out					: out STD_LOGIC;
				event_detect_out			: out STD_LOGIC;
				bl_gate_out					: out STD_LOGIC;
				ed_gate_out					: out STD_LOGIC;
				eventdata_valid			: out STD_LOGIC;
				eventnr_out					: out STD_LOGIC_VECTOR;
				fraction						: out STD_LOGIC_VECTOR;
				energy						: out STD_LOGIC_VECTOR
			);
end MWD_CF_process;
 
architecture Behavioral of MWD_CF_process is
 
	constant	SIGNED_WIDTH		: natural	:= WIDTH + 1;
	constant FRACTION_SIZE		: natural	:= INTERP_CYCLES;-- 	- ZEROX_WINDOW_PWR; --all  interp bits are fraction now !! interp between 2 samples
	constant MAX_RESHAPE_PWR	: natural	:= 2;
 
	component MWD_programmable
	generic(	MAX_MWD_PWR		:	natural);
		Port (rst					: in  STD_LOGIC;
				clk					: in  STD_LOGIC;
				enable				: in  STD_LOGIC;
				program				: in  std_logic;
				mwd_pwr_in			: in  std_logic_vector(7 downto 0);
				data_in				: in  STD_LOGIC_VECTOR;
				correction_in		: in  STD_LOGIC_VECTOR;
				data_out				: out STD_LOGIC_VECTOR
			);
	end component;
 
	component shaper
		Port (rst					: in  STD_LOGIC;
				clk					: in  STD_LOGIC;
				enable				: in  STD_LOGIC;
				program				: in  std_logic;
				data_in				: in  STD_LOGIC_VECTOR;
				correction_in		: in  STD_LOGIC_VECTOR;
				data_out				: out STD_LOGIC_VECTOR
			);
	end component;
 
	component  mux_sre
		Port (rst			: in  STD_LOGIC;
				clk			: in  STD_LOGIC;
				enable		: in  STD_LOGIC;
				selectB		: in  STD_LOGIC;
				a				: in  STD_LOGIC_VECTOR;
				b				: in  STD_LOGIC_VECTOR;
				data_valid	: out	STD_LOGIC;
				q				: out STD_LOGIC_VECTOR
			);
	end component;
 
	COMPONENT CF_process
		generic(	WIDTH							:	natural	:= 1;
					MAX_CF_PWR					:	natural	:=	1;
					MAX_BASELINE_PWR			:	natural	:=	1;
					ZEROX_WINDOW_PWR			:	natural	:=	1;
					ZEROX_THRESHOLD_PWR		:	natural	:=	1;--					INTEGRAL_PWR				:	natural	:=	1;
					INTERP_CYCLES				:	natural	:=	1
				);
		Port (	rst							: in STD_LOGIC;
					clk							: in STD_LOGIC;
					enable						: in STD_LOGIC;
					program						: in STD_LOGIC;
					baseline_enable			: in STD_LOGIC;
					double_CF_in				: in STD_LOGIC;
					data_in						: in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
					threshold_in				: in STD_LOGIC_VECTOR;
					cf_pwr_in					: in STD_LOGIC_VECTOR;
					cf_integral_pwr_in		: in STD_LOGIC_VECTOR;
					baseline_pwr_in			: in STD_LOGIC_VECTOR;
					baseline_inhibit_cnt_in	: in STD_LOGIC_VECTOR;
					event_inhibit_cnt_in		: in STD_LOGIC_VECTOR;
					baseline_out				: out STD_LOGIC_VECTOR;
					clamped_out					: out STD_LOGIC_VECTOR;
					del_clamp_out				: out STD_LOGIC_VECTOR;
					CFdev_clamp_out			: out STD_LOGIC_VECTOR;
					cf_trace_out				: out STD_LOGIC_VECTOR;
					integral						: out STD_LOGIC_VECTOR;
					sample_nr					: out STD_LOGIC_VECTOR;
					zeroX_out					: out STD_LOGIC;
					event_detect_out			: out STD_LOGIC;
					bl_gate_out					: out STD_LOGIC;
					ed_gate_out					: out STD_LOGIC;
					eventdata_valid			: out STD_LOGIC;
					eventnr_out					: out STD_LOGIC_VECTOR;
					fraction						: out STD_LOGIC_VECTOR;
					energy						: out STD_LOGIC_VECTOR
			);
	END COMPONENT;
 
-----------------------------------------------------------------------
 
	signal rst_S								: std_logic := '1';
	signal clk_S								: std_logic := '0';
	signal enable_S							: std_logic := '0';
	signal program_S							: std_logic := '0';
	signal baseline_enable_S				: std_logic := '0';
	signal double_CF_S						: std_logic := '0';
	signal bypass_mwd_S						: std_logic := '0';
	signal bypass_reshape_S					: std_logic := '0';
	signal udata_in_S							: std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
	signal invert_data_in_S					: std_logic := '0';
	signal data_in_S							: std_logic_vector(WIDTH downto 0) := (others	=> '0');
	signal decay_correction_S				: std_logic_vector(decay_correction_in'high downto 0) := (others	=> '0');
	signal reshape_correction_S			: std_logic_vector(reshape_correction_in'high downto 0) := (others	=> '0');
	signal threshold_S						: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal mwd_pwr_S							: STD_LOGIC_VECTOR(7 downto 0)	:= conv_std_logic_vector(5,	8);							-- original default value
	signal cf_pwr_S							: STD_LOGIC_VECTOR(7 downto 0)	:= conv_std_logic_vector(4,	8);							-- original default value
	signal cf_integral_pwr_S				: STD_LOGIC_VECTOR(7 downto 0)	:= conv_std_logic_vector(4,	8);							-- original default value = (mwd_power - 1)
	signal baseline_pwr_S					: STD_LOGIC_VECTOR (7 downto 0)			 := (others	=> '0');
	signal baseline_inhibit_cnt_S			: STD_LOGIC_VECTOR(7 downto 0)	:= conv_std_logic_vector(32,	8);							-- original default value
	signal event_inhibit_cnt_S				: STD_LOGIC_VECTOR(7 downto 0)	:= conv_std_logic_vector(16,	8);							-- original default value
 
	signal short_S								: std_logic_vector(WIDTH downto 0) := (others	=> '0');
	signal reshaped_S							: std_logic_vector(WIDTH downto 0) := (others	=> '0');
	signal mwd_switch_out_S					: std_logic_vector(WIDTH downto 0) := (others	=> '0');
	signal mwd_switch_data_valid_S		: std_logic := '0';
	signal reshape_switch_out_S			: std_logic_vector(WIDTH downto 0) := (others	=> '0');
	signal reshape_switch_data_valid_S	: std_logic := '0';
	signal baseline_S							: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal clamped_S							: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal CFdev_clamp_S						: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal del_clamp_S						: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal cf_trace_S							: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal integral_S							: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal event_detect_S					: std_logic	:= '0';
	signal zeroX_S								: STD_LOGIC	:= '0';
	signal bl_gate_S							: STD_LOGIC	:= '0';
	signal ed_gate_S							: STD_LOGIC	:= '0';
	signal sample_nr_S						: STD_LOGIC_VECTOR(63 downto 0) := (others	=> '0');
	signal eventnr_S							: STD_LOGIC_VECTOR(63 downto 0) := (others	=> '0');
	signal fraction_S							: STD_LOGIC_VECTOR(FRACTION_SIZE - 1 downto 0) := (others	=> '0');
	signal energy_S							: STD_LOGIC_VECTOR(WIDTH downto 0) := (others	=> '0');
	signal eventdata_valid_S				: STD_LOGIC	:= '0';
-----------------------------------------------------------------------
 
begin
 
	mwd : MWD_programmable
		generic map(MAX_MWD_PWR		=> MAX_MWD_PWR)
		port map(rst					=> rst_S,
					clk					=>	clk_S,
					enable				=> enable_S,
					program				=> program_S,
					mwd_pwr_in			=> mwd_pwr_S,
					data_in				=>	data_in_S,
					correction_in		=>	decay_correction_S,
					data_out				=> short_S
				);
 
	mwd_switch	: mux_sre
		port map(rst					=> rst_S,
					clk					=> clk_S,
					enable				=> enable_S,
					selectb				=> bypass_mwd_S,
					a						=> short_S,
					b						=> data_in_S,
					data_valid			=> mwd_switch_data_valid_S,
					q						=> mwd_switch_out_S
				);
 
	reshape : shaper
		port map(rst					=> rst_S,
					clk					=>	clk_S,
					enable				=> mwd_switch_data_valid_S,
					program				=> program_S,
					data_in				=>	mwd_switch_out_S,
					correction_in		=>	reshape_correction_S,
					data_out				=> reshaped_S		
				);
 
	reshape_switch	: mux_sre
		port map(rst					=> rst_S,
					clk					=> clk_S,
					enable				=> mwd_switch_data_valid_S,
					selectb				=> bypass_reshape_S,
					a						=> reshaped_S,
					b						=> mwd_switch_out_S,
					data_valid			=> reshape_switch_data_valid_S,
					q						=> reshape_switch_out_S
				);
 
   CF	: CF_process
		generic map(WIDTH							=>	SIGNED_WIDTH,
						MAX_CF_PWR					=> MAX_CF_PWR,
						MAX_BASELINE_PWR			=>	MAX_BASELINE_PWR,
						ZEROX_WINDOW_PWR			=>	ZEROX_WINDOW_PWR,
						ZEROX_THRESHOLD_PWR		=>	ZEROX_THRESHOLD_PWR,
						INTERP_CYCLES				=>	INTERP_CYCLES
						)
		PORT MAP(	rst							=> rst_S,
						clk							=> clk_S,
						enable						=> reshape_switch_data_valid_S,
						program						=>	program_S,
						baseline_enable			=> baseline_enable_S,
						double_CF_in				=> double_CF_S,
						data_in						=> reshape_switch_out_S,
						threshold_in				=>	threshold_S,
						cf_pwr_in					=>	cf_pwr_S,
						cf_integral_pwr_in		=>	cf_integral_pwr_S,
						baseline_pwr_in			=>	baseline_pwr_S,
						baseline_inhibit_cnt_in	=>	baseline_inhibit_cnt_S,
						event_inhibit_cnt_in		=>	event_inhibit_cnt_S,
						baseline_out				=>	baseline_S,
						clamped_out					=>	clamped_S,
						del_clamp_out				=>	del_clamp_S,
						CFdev_clamp_out			=>	CFdev_clamp_S,
						cf_trace_out				=>	cf_trace_S,
						integral						=>	integral_S,
						sample_nr					=> sample_nr_S,
						zeroX_out					=>	zeroX_S,
						event_detect_out			=>	event_detect_S,
						bl_gate_out					=>	bl_gate_S,
						ed_gate_out					=>	ed_gate_S,
						eventdata_valid			=>	eventdata_valid_S,
						eventnr_out					=>	eventnr_S,
						fraction						=>	fraction_S,
						energy						=>	energy_S
					);
 
		rst_S							<=	rst;
		clk_S							<=	clk;
		program_S					<=	program;
		baseline_enable_S			<=	baseline_enable;
		double_CF_S					<= double_CF_in;
		bypass_mwd_S				<=	bypass_mwd;
		bypass_reshape_S			<=	bypass_reshape;
		invert_data_in_S			<= invert_data_in;
 
		data_in_S 					<= conv_std_logic_vector(conv_integer(unsigned(udata_in_S)), SIGNED_WIDTH) when invert_data_in_S = '0'
											else conv_std_logic_vector(- conv_integer(unsigned(udata_in_S)), SIGNED_WIDTH);
 
		decay_correction_S		<=	decay_correction_in;
		reshape_correction_S		<=	reshape_correction_in;
		threshold_S					<=	'0' & threshold_in;	-- now it's 17 bit
		mwd_pwr_S					<= mwd_pwr_in;
		cf_pwr_S						<= cf_pwr_in;
		cf_integral_pwr_S			<= cf_integral_pwr_in;
		baseline_pwr_S				<=	baseline_pwr_in;
		baseline_inhibit_cnt_S	<=	baseline_inhibit_cnt_in;
		event_inhibit_cnt_S		<=	event_inhibit_cnt_in;
 
 
		mwd_switch_out				<=	reshape_switch_out_S;
		baseline_out				<=	baseline_S;
		clamped_out					<=	clamped_S;
		del_clamp_out				<=	del_clamp_S;
		CFdev_clamp_out			<=	CFdev_clamp_S;
		cf_trace_out				<=	cf_trace_S;
		integral						<= integral_S;
		sample_nr					<=	sample_nr_S;
		zeroX_out					<=	zeroX_S;
		event_detect_out			<=	event_detect_S;
		bl_gate_out					<=	bl_gate_S;
		ed_gate_out					<=	ed_gate_S;
		eventdata_valid			<= eventdata_valid_S;
		eventnr_out					<= eventnr_S;
		fraction						<= fraction_S;
		energy						<=	energy_S;
 
--		fb_window_size	<=	fb_window_size_S;
 
		-----------------------------------------------------------------------------------
 
--	sync : process(clk_S)	-- introduced to compensate for synchronous resets (1 clock cycle delay)
--	begin
--		if (clk_S'event and clk_S = '1') then
			enable_S		<=	enable;
			udata_in_S	<=	data_in;	-- add a sign bit to avoid disaster
--		end if;
--	end process;
 
end Behavioral;