Subversion Repositories pulse_processing_algorithm

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#
# Xilinx Core Generator version K.39
# Date: Mon Jul 06 12:32:44 2009
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s50
SET devicefamily = spartan3
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Edif
SET package = pq208
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Asynchronous_FIFO family Xilinx,_Inc. 5.1
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=blk_asy_fifo_1023x16
CSET create_rpm=true
CSET fifo_depth=2047
CSET input_data_width=16
CSET memory_type=block
CSET read_acknowledge=false
CSET read_acknowledge_sense=active_high
CSET read_count=true
CSET read_count_width=10
CSET read_error=false
CSET read_error_sense=active_high
CSET write_acknowledge=false
CSET write_acknowledge_sense=active_high
CSET write_count=true
CSET write_count_width=10
CSET write_error=false
CSET write_error_sense=active_high
# END Parameters
GENERATE
# CRC: 7604bd19