Subversion Repositories pulse_processing_algorithm

# Xilinx CORE Generator 6.3.03i
# Username = th
# COREGenPath = C:\ISE6.3\coregen
# ProjectPath = C:\projekte\sis3320\xilinx\work_ddr2_test\sis3320adc
# ExpandedProjectPath = C:\projekte\sis3320\xilinx\work_ddr2_test\sis3320adc
# OverwriteFiles = true
# Core name: blk_asy_fifo_511x32
# Number of Primitives in design: 336
# Number of CLBs used in design: 24
# Number of Slices used in design: 79
# Number of LUT sites used in design: 102
# Number of LUTs used in design: 102
# Number of REG used in design: 139
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 1
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 2
# Huset "blk_asy_fifo_511x32/control/rd_blk" = (0, 0) to (4, 3) in CLBs
# Huset "blk_asy_fifo_511x32/control/wr_blk" = (0, 0) to (4, 3) in CLBs
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Asynchronous_FIFO Spartan3 Xilinx,_Inc. 5.1
CSET read_error_sense = active_high
CSET read_count_width = 9
CSET write_acknowledge = false
CSET create_rpm = true
CSET read_acknowledge = false
CSET read_count = true
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = block
CSET read_error = false
CSET fifo_depth = 511
CSET component_name = blk_asy_fifo_511x32
CSET input_data_width = 32
CSET write_count = true
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 9
GENERATE