Subversion Repositories pulse_processing_algorithm

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--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
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-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	compare_a2b
-- Description	:	Signed comparator of input A-to-B
--	Inputs		:	
--	Outputs		:	
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--	Generics		:	
--	Parameters	:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
 
 
entity compare_a2b is
	Port (	clk	: std_logic;
				a		: in	STD_LOGIC_VECTOR;
				b		: in	STD_LOGIC_VECTOR;
				lt	 	: out	STD_LOGIC;
				gt	 	: out	STD_LOGIC
			);
end compare_a2b;
 
architecture Behavioral of compare_a2b is
 
	constant WIDTH	: natural	:= a'length;
 
	signal clk_S	: std_logic := '0';
	signal a_S		: std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
	signal b_S		: std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
	signal lt_S		: std_logic := '0';
	signal gt_S		: std_logic := '0';
 
 
begin
	clk_S	<= clk;
	a_S	<= a;
	b_S	<= b;
	lt		<= lt_S;
	gt		<= gt_S;
 
	process( clk_S, a_S, b_S)
	begin
		if (clk_S'event and clk_S = '1') then
			if (a_S > b_S) then
				gt_S	<=	'1';
				lt_S	<=	'0';
			else
				if (a_S < b_S) then
					gt_S	<=	'0';
					lt_S	<=	'1';
				else
					gt_S	<=	'0';
					lt_S	<=	'0';
				end if;
			end if;
		end if;
	end process;
end Behavioral;