Subversion Repositories pulse_processing_algorithm

--******************************************************************************
--
--  Xilinx, Inc. 2002                 www.xilinx.com
--
--  XAPP 253 - Synthesizable DDR SDRAM Controller
--
--*******************************************************************************
--
--  File name :       controller.vhd
--
--  Description :     
--                    Main DDR SDRAM controller block. This includes the following
--                    features:
--                    - The controller state machine that controls the 
--                    initialization process upon power up, as well as the 
--                    read, write, and refresh commands. 
--                    - Accepts and decodes the user commands.
--                    - Generates the address and Bank address signals
--                    - Generates control signals for other modules, including
--                    the control signals for the dqs_en block.
--
-- 
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
 
entity controller_ddr2_iobs is
port(
    clk0             : in std_logic;
    clk180           : in std_logic;
    ddr_rasb_cntrl   : in std_logic;
    ddr_casb_cntrl   : in std_logic;
    ddr_web_cntrl    : in std_logic;
    ddr_cke_cntrl    : in std_logic;
    ddr_csb_cntrl    : in std_logic;
    ddr_ODT_cntrl    : in std_logic;
    ddr_address_cntrl: in std_logic_vector(12 downto 0);
    ddr_ba_cntrl     : in std_logic_vector(1 downto 0);
    rst_dqs_div_int  : in std_logic;
    ddr_rasb         : out std_logic;
    ddr_ODT0         : out std_logic;
    ddr_casb         : out std_logic;
    ddr_web          : out std_logic;
    ddr_ba           : out std_logic_vector(1 downto 0);
    ddr_address      : out std_logic_vector(15 downto 0);
    ddr_cke          : out std_logic;
    ddr_csb          : out std_logic;
    rst_dqs_div      : out std_logic;
   rst_dqs_div_iob   : inout std_logic 
--    rst_dqs_div_in   : in std_logic;
--    rst_dqs_div_out  : out std_logic
 
);
end controller_ddr2_iobs;
 
 
architecture arc_controller_ddr2_iobs of controller_ddr2_iobs is
 
attribute xc_props : string;
attribute syn_keep : boolean;
 
 
component IBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
component OBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
component IBUF
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
component OBUF
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
 
component FD
   port(
      Q                              :  out   STD_LOGIC;
      D                              :  in    STD_LOGIC;
      C                              :  in    STD_LOGIC);
end component;
 
component OFD
   port(
      Q                              :  out   STD_LOGIC;
      D                              :  in    STD_LOGIC;
      C                              :  in    STD_LOGIC);
end component;
 
--component OBUFT
--port(
--      I : in std_logic;
--      T : in std_logic;
--      O : out std_logic);
--end component;
 
 
---- **************************************************
---- iob attributes for instantiated FD components
---- **************************************************
 
 
--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL
--signal rst_dqs_div_out     : std_logic;
 
 
--signal GND        : std_logic;
--signal ddr_web_q  : std_logic;
--signal ddr_rasb_q : std_logic;
--signal ddr_casb_q : std_logic;
 
--signal ddr_ba_q : std_logic_vector(1 downto 0);
--signal ddr_address_q : std_logic_vector(15 downto 0);
--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL
 
 
 
--attribute xc_props of iob_web:  label is "IOB=TRUE";
--attribute xc_props of iob_rasb: label is "IOB=TRUE";
--attribute xc_props of iob_casb: label is "IOB=TRUE";
 
 
--attribute xc_props of iob_addr0: label is "IOB=TRUE";
--attribute xc_props of iob_addr1: label is "IOB=TRUE";
--attribute xc_props of iob_addr2: label is "IOB=TRUE";
--attribute xc_props of iob_addr3: label is "IOB=TRUE";
--attribute xc_props of iob_addr4: label is "IOB=TRUE";
--attribute xc_props of iob_addr5: label is "IOB=TRUE";
--attribute xc_props of iob_addr6: label is "IOB=TRUE";
--attribute xc_props of iob_addr7: label is "IOB=TRUE";
--attribute xc_props of iob_addr8: label is "IOB=TRUE";
--attribute xc_props of iob_addr9: label is "IOB=TRUE";
--attribute xc_props of iob_addr10: label is "IOB=TRUE";
--attribute xc_props of iob_addr11: label is "IOB=TRUE";
--attribute xc_props of iob_addr12: label is "IOB=TRUE";
 
--attribute xc_props of iob_ba0: label is "IOB=TRUE";
--attribute xc_props of iob_ba1: label is "IOB=TRUE";
 
begin
 
--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL
--GND <= '0';
 
 
---- ******************************************* ----
----  Includes the instantiation of FD for cntrl ----
----            signals                          ----
---- ******************************************* ----
 
iob_web : OFD port map (
                         Q    => ddr_web,
                         D    => ddr_web_cntrl,
                         C    => clk180);
 
iob_rasb : OFD port map (
                         Q    => ddr_rasb,
                         D    => ddr_rasb_cntrl,
                         C    => clk180);
 
iob_casb : OFD port map (
                         Q    => ddr_casb,
                         D    => ddr_casb_cntrl,
                         C    => clk180);                                                  
 
 
--iob_casb : FD port map (
--                         Q    => ddr_casb_q,
--                         D    => ddr_casb_cntrl,
--                         C    => clk180);                                                  
 
 
---- ************************************* ----
----  Output buffers for control signals   ----
---- ************************************* ----
 
--r0 : OBUF port map (
--                     I => ddr_web_q,
--                     O => ddr_web);
 
--r1 : OBUF port map (
--                     I => ddr_rasb_q,
--                     O => ddr_rasb);
 
--r2 : OBUF port map (
--                     I => ddr_casb_q,
--                     O => ddr_casb);
 
r3 : OBUF port map (
                     I => ddr_cke_cntrl,
                     O => ddr_cke);
 
r4 : OBUF port map (
                     I => ddr_csb_cntrl,
                     O => ddr_csb);
 
r40 : OBUF port map (
                     I => ddr_ODT_cntrl,
                     O => ddr_ODT0);
 
 
 
---- ************************************* ----
----  Output buffers for address signals   ----
---- ************************************* ----
 
 
 
 
--iob_addr0 : FD port map (
--                         Q    => ddr_address_q(0),
--                         D    => ddr_address_cntrl(0),
--                         C    => clk180);
 
iob_addr0 : OFD port map (
                         Q    => ddr_address(0),
                         D    => ddr_address_cntrl(0),
                         C    => clk180);
 
iob_addr1 : OFD port map (
                         Q    => ddr_address(1),
                         D    => ddr_address_cntrl(1),
                         C    => clk180);
 
iob_addr2 : OFD port map (
                         Q    => ddr_address(2),
                         D    => ddr_address_cntrl(2),
                         C    => clk180);
 
iob_addr3 : OFD port map (
                         Q    => ddr_address(3),
                         D    => ddr_address_cntrl(3),
                         C    => clk180);
 
iob_addr4 : OFD port map (
                         Q    => ddr_address(4),
                         D    => ddr_address_cntrl(4),
                         C    => clk180);
 
iob_addr5 : OFD port map (
                         Q    => ddr_address(5),
                         D    => ddr_address_cntrl(5),
                         C    => clk180);
 
iob_addr6 : OFD port map (
                         Q    => ddr_address(6),
                         D    => ddr_address_cntrl(6),
                         C    => clk180);
 
iob_addr7 : OFD port map (
                         Q    => ddr_address(7),
                         D    => ddr_address_cntrl(7),
                         C    => clk180);
 
iob_addr8 : OFD port map (
                         Q    => ddr_address(8),
                         D    => ddr_address_cntrl(8),
                         C    => clk180);
 
iob_addr9 : OFD port map (
                         Q    => ddr_address(9),
                         D    => ddr_address_cntrl(9),
                         C    => clk180);
 
iob_addr10 : OFD port map (
                         Q    => ddr_address(10),
                         D    => ddr_address_cntrl(10),
                         C    => clk180);
 
iob_addr11 : OFD port map (
                         Q    => ddr_address(11),
                         D    => ddr_address_cntrl(11),
                         C    => clk180);
 
iob_addr12 : OFD port map (
                         Q    => ddr_address(12),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
iob_addr13 : OFD port map (
                         Q    => ddr_address(13),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
iob_addr14 : OFD port map (
                         Q    => ddr_address(14),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
 
iob_addr15 : OFD port map (
                         Q    => ddr_address(15),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
 
 
--r5 : OBUF port map (
--                     I => ddr_address_q(0),
--                     O => ddr_address(0));
 
--r6 : OBUF port map (
--                     I => ddr_address_q(1),
--                     O => ddr_address(1));
 
--r7 : OBUF port map (
--                     I => ddr_address_q(2),
--                     O => ddr_address(2));
 
--r8 : OBUF port map (
--                     I => ddr_address_q(3),
--                     O => ddr_address(3));
 
--r9 : OBUF port map (
--                     I => ddr_address_q(4),
--                     O => ddr_address(4));
 
--r10 : OBUF port map (
--                     I => ddr_address_q(5),
--                     O => ddr_address(5));
 
--r11 : OBUF port map (
--                     I => ddr_address_q(6),
--                     O => ddr_address(6));
 
--r12 : OBUF port map (
--                     I => ddr_address_q(7),
--                     O => ddr_address(7));
 
--r13 : OBUF port map (
--                     I => ddr_address_q(8),
--                     O => ddr_address(8));
 
--r14 : OBUF port map (
--                     I => ddr_address_q(9),
--                     O => ddr_address(9));
 
--r15 : OBUF port map (
--                     I => ddr_address_q(10),
--                     O => ddr_address(10));
 
--r16 : OBUF port map (
--                     I => ddr_address_q(11),
--                     O => ddr_address(11));
 
--r17 : OBUF port map (
 --                    I => ddr_address_q(12),
 --                    O => ddr_address(12));
 
 
 
 
iob_ba0 : FD port map (
                         Q    => ddr_ba(0),
                         D    => ddr_ba_cntrl(0),
                         C    => clk180);
 
iob_ba1 : FD port map (
                         Q    => ddr_ba(1),
                         D    => ddr_ba_cntrl(1),
                         C    => clk180);
 
--r18 : OBUF port map (
--                     I => ddr_ba_q(0),
--                     O => ddr_ba(0));
 
--r19 : OBUF port map (
--                     I => ddr_ba_q(1),
--                     O => ddr_ba(1));
 
 
 
---rst_iob_inbuf  :  IBUF port map                        
rst_iob_inbuf  :  IBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_iob,
                              O  => rst_dqs_div);
 
 
---rst_iob_outbuf  :  OBUF port map                            
rst_iob_outbuf  :  OBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_int,
--                              O  => rst_dqs_div_out);
                              O  => rst_dqs_div_iob);
 
 
 
 
 
 
--U3 : OBUFT  port map ( I => rst_dqs_div_out, 
--                       T => '0' ,
--                       O => rst_dqs_div_iob);
 
 
 
 
 
end arc_controller_ddr2_iobs;