Subversion Repositories pulse_processing_algorithm

-----------------------------------------------------------------------------------------------
--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	dff_re.vhd
-- Description	:	D-FlipFlop with Reset & Enable; variable width
--						
-----------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity dff_re is
   Port (	rst			: in  STD_LOGIC;
				clk			: in  STD_LOGIC;
				enable		: in  STD_LOGIC;
				data_valid	: out	STD_LOGIC;
				d				: in  STD_LOGIC_VECTOR;
				q				: out STD_LOGIC_VECTOR
				);
end dff_re;
 
architecture Behavioral of dff_re is
	constant	WIDTH		: natural := d'length;
   signal rst_S			: std_logic := '1';
	signal clk_S			: std_logic;
	signal enable_S		: std_logic;
	signal data_valid_S	: std_logic := '0';
	signal d_S				: STD_LOGIC_VECTOR(d'high downto 0);
	signal q_S				: STD_LOGIC_VECTOR(q'high downto 0) := (others => '0');
 
begin
	rst_S				<= rst;
	clk_S				<= clk;
	enable_S			<= enable;
	data_valid		<=	data_valid_S;
	d_S				<= d;
	q					<= q_S;
 
	process(clk_S, rst_S, enable_S)
	begin
		if rising_edge(clk_S) then
			if rst_S='1' then
				q_S(WIDTH - 1 downto 0) <= (others => '0');
				data_valid_S	<= '0';
			elsif (enable_S = '1') then 
				q_S 				<= d_S;
				data_valid_S	<= '1';
			else
				data_valid_S	<= '0';
			end if;
		end if;
	end process;
end Behavioral;