Subversion Repositories pulse_processing_algorithm

 
--  fifo_wr_en is derived  by ORing -
--  "rst_dqs_div" , delayed rst_dqs_div with negedge of the ddr_dqs 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
 
 
 
                  ENTITY fifo_1_wr_en IS
-- Declarations
port (
 
		clk 		:  in std_logic;
		rst_dqs_delay_n : in std_logic;
 	   	reset		:	in std_logic; 
		din		:	in std_logic;
		dout		:	out std_logic
	  );
END fifo_1_wr_en ;
 
-- hds interface_end
ARCHITECTURE fifo_1_wr_en OF fifo_1_wr_en IS
 
component FDCE
    port(
      Q                              :	out   STD_LOGIC;
      C                              :	in    STD_LOGIC;
      CE                             :	in    STD_LOGIC;
      CLR                            :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC     
      );
end component;
 
 
 
attribute syn_keep : boolean;  -- Using Syn_Keep Derictive
 
--signal	din_delay	:	STD_ULOGIC;
signal	din_delay_1	:	STD_LOGIC;
 
signal  	TIE_HIGH    : 	STD_ULOGIC;
 
signal dout0 : STD_ULOGIC; 
signal rst_dqs_delay : std_logic;
 
BEGIN
 
	rst_dqs_delay <= not rst_dqs_delay_n;	
	dout0 <= din and rst_dqs_delay_n;
	dout <= rst_dqs_delay or din_delay_1;
	TIE_HIGH <= '1';
 
 
delay_ff_1 : FDCE port map (
                      Q   => din_delay_1,
                      C   => clk,
                      CE  => TIE_HIGH,
                      CLR => reset,
                      D   => dout0
                     );
 
 
 
END fifo_1_wr_en;