Subversion Repositories pulse_processing_algorithm

-----------------------------------------------------------------------------------------------
--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	gate_generator.vhd 
-- Description	:	Generate 2 independent gating signals upon event-detection
--						bl-gate == '1' enables collection of baseline data/samples
--						ed-gate == '1' enables event detection
--						Both are disabled at an event and remain inactive for seperate counts
-----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
 
entity gate_generator is
	Port (	rst							: in  STD_LOGIC;
				clk							: in  STD_LOGIC;
				enable						: in  STD_LOGIC;
				program						: in  STD_LOGIC;
				baseline_enable			: in  STD_LOGIC;
				event_in						: in	STD_LOGIC;
				baseline_inhibit_cnt_in	: in STD_LOGIC_VECTOR;
				event_inhibit_cnt_in		: in STD_LOGIC_VECTOR;
				bl_gate_out					: out	STD_LOGIC;			-- baseline gate-signal
				ed_gate_out					: out	STD_LOGIC			-- baseline gating inhibited because of event
			);
end gate_generator;
 
architecture Behavioral of gate_generator is
 
	type Gate_state_type is (gate_idle, gate_inhibit, gate_enable);
 
	signal rst_S						: std_logic := '1';
	signal clk_S						: std_logic := '0';
	signal enable_S					: std_logic := '0';
	signal program_S					: std_logic := '0';
	signal baseline_enable_S		: std_logic := '0';
	signal event_in_S					: std_logic := '0';
--	signal baseline_inhibit_set_S	: STD_LOGIC_VECTOR(7 downto 0)	:= conv_std_logic_vector(32,	8);	-- original default value
--	signal event_inhibit_set_S		: STD_LOGIC_VECTOR(7 downto 0)	:= conv_std_logic_vector(20,	8);	-- original default value
	signal bl_gate_S					: std_logic := '0';
	signal ed_gate_S					: std_logic := '0';
--	baseline_inhibit_counter; inhibits baseline sampling at reset or event
--	signal bl_inhibit_cnt_S			: std_logic_vector(M4_PWR+ 1 downto 0) := conv_std_logic_vector(BL_GATE_COUNT,M4_PWR + 2);
	signal bl_inhibit_cnt_S			: std_logic_vector(7 downto 0)	:= conv_std_logic_vector(32,	8);	-- original default value;
	signal bl_inhibit_val_S			: std_logic_vector(7 downto 0)	:= conv_std_logic_vector(32,	8);	-- original default value;
--	signal bl_gate_cnt_S				: std_logic_vector(M4_PWR+ 1 downto 0) := (others => '0'); --conv_std_logic_vector(BL_GATE_COUNT,M4_PWR + 2);
--	event_detect_inhibit_counter; inhibits baseline sampling during event
--	signal ed_inhib_cnt_S			: std_logic_vector(BASE_WINDOW_PWR+ 1 downto 0) := (others => '0'); -- conv_std_logic_vector(ED_INHIBIT_COUNT,BASE_WINDOW_PWR + 2);
	signal ed_inhibit_cnt_S			: std_logic_vector(7 downto 0)	:= conv_std_logic_vector(32,	8);	-- original default value;
	signal ed_inhibit_val_S			: std_logic_vector(7 downto 0)	:= conv_std_logic_vector(32,	8);	-- original default value;
 
begin
 
	rst_S							<=	rst;
	clk_S							<=	clk;
	enable_S 					<= enable;
	program_S					<=	program;
	baseline_enable_S			<=	baseline_enable;	-- allready clocked in Feature_extraction.vhd
	event_in_S					<= event_in;
	bl_gate_out					<= bl_gate_S;
	ed_gate_out					<= ed_gate_S;
 
 
	gate_count : process(clk_S, enable_S, event_in_S, baseline_enable_S)
	begin
		if (clk_S'event and clk_S = '1') then
			if (rst_S = '1') or (program_S = '1') then
				bl_inhibit_val_S		<= baseline_inhibit_cnt_in;
				ed_inhibit_val_S 		<= event_inhibit_cnt_in;
			elsif enable_S = '1' then
 
				if (baseline_enable_S = '1') then
				--	on eventdetect, initialize event_inhibition for a fixed period
					if (event_in_S = '1') then
						ed_inhibit_cnt_S 		<= ed_inhibit_val_S;
				--	event_inhibition for a fixed period
					elsif (ed_inhibit_cnt_S > 0) then
						ed_inhibit_cnt_S <= ed_inhibit_cnt_S - 1;
					end if;
				--	on eventdetect, initialize baseline_inhibition for a fixed period
					if (event_in_S = '1') then
						bl_inhibit_cnt_S		<= bl_inhibit_val_S;
				--	event_inhibition for a fixed period
					elsif (bl_inhibit_cnt_S > 0) then
						bl_inhibit_cnt_S <= bl_inhibit_cnt_S - 1;
					end if;
				end if;
			end if;
		end if;
	end process;
 
	gate : process(clk_S, enable_S, event_in_S)
	begin
		if (clk_S'event and clk_S = '1') then
			if (enable_S = '1') and (bl_inhibit_cnt_S = 0) and (event_in_S = '0') and (baseline_enable_S = '1') then
				bl_gate_S <= '1';
			else
				bl_gate_S <= '0';
			end if;
 
			if (enable_S = '1') and (ed_inhibit_cnt_S = 0) and (event_in_S = '0')  and (baseline_enable_S = '1') then
				ed_gate_S <= '1';
			else
				ed_gate_S <= '0';
			end if;
		end if;
	end process;
 
end Behavioral;