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[/] [pulse_processing_algorithm/] [output_select.vhd] - Rev 2
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----------------------------------------------------------------------------------------------- -- -- Copyright (C) 2011 Peter Lemmens, PANDA collaboration -- p.j.j.lemmens@rug.nl -- http://www-panda.gsi.de -- -- As a reference, please use: -- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner, -- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter" -- Nuclear Inst. and Methods in Physics Research, A .... -- -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA -- ----------------------------------------------------------------------------------------------- -- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands -- Author : P.J.J. Lemmens -- Design Name : Feature Extraction -- Module Name : data_select.vhd -- Description : The data-selector is in essence a DEBUG-feature that enables the selection -- of 1 of 16 busses for output; most giving continuous data. -- -- 0 'echo-mode' copying input data to output to see if anything works at all -- 1 mwd (moving window deconv) output = CF-input -- 2 baseline value -- 3 CF-input signal clamped to zero -- 4 CF-input signal clamped to zero and delayed -- 5 CF-input signal clamped to zero and divided by 4 (or 2) and inverted -- 6 CF result -- 7 CF-input signal integrated -- 8 zero-crossing detection signal -- 9 event-detection signal -- 10 gating signal -- 11 energy/amplitude/peak-value of signal at an event -- 12 samplenr (lower 16-bits) when an event is detected -- 13 samplenr (lower 16-bits) when an event is detected -- 14 time fraction (right alligned) -- 15 multiplexed event feature packet -- ----------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; use IEEE.STD_LOGIC_ARITH.ALL; entity output_select is PORT ( clk : in std_logic; output_select : in std_logic_vector; indata_in : in std_logic_vector; -- Feature Extraction data_in mwd_in : in std_logic_vector; baseline_in : in std_logic_vector; clamped_in : in std_logic_vector; del_clamp_in : in std_logic_vector; CFdev_clamp_in : in std_logic_vector; cf_trace_in : in std_logic_vector; integral_in : in std_logic_vector; zerox_in : in std_logic; eventdetect_in : in std_logic; gate_in : in std_logic; energy_in : in std_logic_vector; mux_data_in : in std_logic_vector; samplenr_in : in STD_LOGIC_VECTOR; fraction_in : in STD_LOGIC_VECTOR; mux_data_valid_in : in std_logic; fe_data_valid : in std_logic; dataword_out : out std_logic_vector; data_out_valid : out std_logic ); end output_select; architecture Behavioral of output_select is constant WIDTH : natural := indata_in'length; signal clk_S : std_logic := '0'; signal output_select_S : std_logic_vector(output_select'high downto 0) := (others => '0'); signal indata_in_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0'); signal mwd_in_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0'); signal baseline_in_S : std_logic_vector(WIDTH - 1 downto 0); signal clamped_in_S : std_logic_vector(WIDTH - 1 downto 0); signal del_clamp_in_S : std_logic_vector(WIDTH - 1 downto 0); signal CFdev_clamp_in_S : std_logic_vector(WIDTH - 1 downto 0); signal cf_trace_in_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0); signal integral_in_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0); signal zeroX_in_S : STD_LOGIC; signal eventdetect_in_S : STD_LOGIC; signal gate_in_S : STD_LOGIC; signal energy_in_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0); signal dataLSB_out_S : std_logic_vector(7 downto 0) := (others => '0'); signal dataMSB_out_S : std_logic_vector(7 downto 0) := (others => '0'); signal uar_data_valid_in_S : std_logic; signal mux_data_in_S : std_logic_vector(15 downto 0) := (others => '0'); signal samplenr_in_S : std_logic_vector(63 downto 0) := (others => '0'); signal fraction_in_S : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); signal mux_data_in_valid_S : std_logic; signal dataword_out_S : std_logic_vector(15 downto 0) := (others => '0'); signal intermed_valid_S : std_logic; signal data_out_valid_S : std_logic; begin clk_S <= clk; output_select_S <= output_select; indata_in_S <= indata_in; mwd_in_S <= mwd_in; baseline_in_S <= baseline_in; clamped_in_S <= clamped_in; del_clamp_in_S <= del_clamp_in; CFdev_clamp_in_S <= CFdev_clamp_in; cf_trace_in_S <= cf_trace_in; integral_in_S <= integral_in; zerox_in_S <= zerox_in; eventdetect_in_S <= eventdetect_in; gate_in_S <= gate_in; energy_in_S <= energy_in; mux_data_in_S <= mux_data_in; samplenr_in_S <= samplenr_in; fraction_in_S(fraction_in'high downto 0) <= fraction_in; fraction_in_S(fraction_in_S'high downto fraction_in'high + 1) <= (others => '0'); mux_data_in_valid_S <= mux_data_valid_in; uar_data_valid_in_S <= fe_data_valid; dataword_out <= dataword_out_S; data_out_valid <= data_out_valid_S; select_proc : process(clk_S) --, output_select_S, indata_in_S, baseline_in_S, clamped_in_S, del_clamp_in_S, CFdev_clamp_in_S, --cf_trace_in_S, integral_in_S, zeroX_in_S, gate_in_S, energy_in_S, mux_data_in_S, mux_data_in_valid_S) begin if (clk_S'event and clk_S = '1') then -- clocking this SOB gives 2 extra delays... laat maar case conv_integer(output_select_S) is when 0 => dataLSB_out_S <= indata_in_S(7 downto 0); dataMSB_out_S <= indata_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 1 => dataLSB_out_S <= mwd_in_S(7 downto 0); dataMSB_out_S <= mwd_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 2 => dataLSB_out_S <= baseline_in_S(7 downto 0); dataMSB_out_S <= baseline_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 3 => dataLSB_out_S <= clamped_in_S(7 downto 0); dataMSB_out_S <= clamped_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 4 => dataLSB_out_S <= del_clamp_in_S(7 downto 0); dataMSB_out_S <= del_clamp_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 5 => dataLSB_out_S <= CFdev_clamp_in_S(7 downto 0); dataMSB_out_S <= CFdev_clamp_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 6 => dataLSB_out_S <= cf_trace_in_S(7 downto 0); dataMSB_out_S <= cf_trace_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 7 => dataLSB_out_S <= integral_in_S(7 downto 0); dataMSB_out_S <= integral_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 8 => dataLSB_out_S(7) <= zeroX_in_S; dataLSB_out_S(6 downto 0) <= (others => '0'); dataMSB_out_S <= (others => '0'); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 9 => dataLSB_out_S(7) <= eventdetect_in_S; dataLSB_out_S(6 downto 0) <= (others => '0'); dataMSB_out_S <= (others => '0'); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 10 => dataLSB_out_S(7) <= gate_in_S; dataLSB_out_S(6 downto 0) <= (others => '0'); dataMSB_out_S <= (others => '0'); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 11 => dataLSB_out_S <= energy_in_S(7 downto 0); dataMSB_out_S <= energy_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 12 => dataLSB_out_S <= samplenr_in_S(7 downto 0); dataMSB_out_S <= samplenr_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 13 => dataLSB_out_S <= samplenr_in_S(23 downto 16); dataMSB_out_S <= samplenr_in_S(31 downto 24); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when 14 => dataLSB_out_S <= fraction_in_S(7 downto 0); dataMSB_out_S <= fraction_in_S(15 downto 8); intermed_valid_S <= uar_data_valid_in_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; when others => dataLSB_out_S <= mux_data_in_S(7 downto 0); dataMSB_out_S <= mux_data_in_S(15 downto 8); intermed_valid_S <= mux_data_in_valid_S; dataword_out_S(7 downto 0) <= dataMSB_out_S; dataword_out_S(15 downto 8) <= dataLSB_out_S; data_out_valid_S <= intermed_valid_S; end case; end if; end process; end Behavioral;