Subversion Repositories pulse_processing_algorithm

-- fifo_rd_addr gray counter with synchronous reset
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
 
 
 
ENTITY  rd_gray_cntr IS
	port (
			clk 				: 	in std_logic;         
			reset				:	in std_logic;
			cnt_en			        :	in std_logic; 
                        rgc_gcnt			:	out	std_logic_vector(3 downto 0)
 
		  );
END rd_gray_cntr;
 
ARCHITECTURE rd_gray_cntr OF rd_gray_cntr IS
 
component FDRE
    port(
      Q                              :	out   STD_ULOGIC;
      C                              :	in    STD_ULOGIC;
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      R			             :	in    STD_ULOGIC
      );
end component;
 
-- gray encoded signals
 
signal  d0	:	STD_ULOGIC;
signal  d1	:	STD_ULOGIC;
signal  d2	:	STD_ULOGIC;	
signal  d3	:	STD_ULOGIC;
signal  gc_int0 :  std_logic_vector(3 downto 0);
 
 
BEGIN
 
    rgc_gcnt <= gc_int0(3 downto 0);
 
 
    d0 <= ( (not gc_int0(3)) and (not gc_int0(2)) and (not gc_int0(1)) ) or ( gc_int0(3) and gc_int0(2) and (not gc_int0(1)) ) or ( gc_int0(3) and (not gc_int0(2)) and gc_int0(1) ) or ( (not gc_int0(3)) and gc_int0(2) and gc_int0(1) );
    d1 <= ( gc_int0(1) and (not gc_int0(0)) ) or ( (not gc_int0(3)) and (not gc_int0(2)) and gc_int0(0) ) or ( gc_int0(3) and gc_int0(2) and gc_int0(0) );
    d2 <= ( (not gc_int0(3)) and gc_int0(1) and (not gc_int0(0)) ) or ( gc_int0(2) and (not gc_int0(1)) ) or ( gc_int0(2) and gc_int0(0) );
    d3 <= ( gc_int0(2) and (not gc_int0(1)) and (not gc_int0(0)) ) or ( gc_int0(3) and gc_int0(0) ) or ( gc_int0(3) and gc_int0(1) );
 
 
bit0 : FDRE port map (
                      Q   => gc_int0(0),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d0,
			    R   => reset
                     );
 
bit1 : FDRE port map (
                      Q   => gc_int0(1),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d1,
			    R   => reset
                     );
 
bit2 : FDRE port map (
                      Q   => gc_int0(2),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d2,
			    R   => reset
                     );
 
bit3 : FDRE port map (
                      Q   => gc_int0(3),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d3,
		      R   => reset
                     );
 
END rd_gray_cntr;