Subversion Repositories pulse_processing_algorithm

--******************************************************************************
--
--  Xilinx, Inc. 2002                 www.xilinx.com
--
--
--*******************************************************************************
--
--  File name :       s3_ddr_iob.vhd
--
--  Description :     This module instantiates DDR IOB output flip-flops, an 
--                    output buffer with registered tri-state, and an input buffer  
--                    for a single data bit. The DDR input flip-flops are not used
--                    since data is captured in the CLB flip-flops. 
--                    
--  Date - revision : 07/28/2003
--
--
-- 
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
 
entity s3_ddr_iob is 
port (
      ddr_dq_inout       : inout std_logic; --Bi-directional SDRAM data bus
      write_data_falling : in std_logic;    --Transmit data, output on falling edge
      write_data_rising  : in std_logic;    --Transmit data, output on rising edge
      read_dq_ce  : in std_logic;    --Transmit data, output on rising edge
      clk_rx  : in std_logic;    --
      read_data_in_rising   : out std_logic;   --Receive data, captured on rising edge
      read_data_in_falling  : out std_logic;   --Receive data, captured on falling edge
--old      read_data_in       : out std_logic;   -- Received data
      clk90              : in std_logic;    --Clock 90
      clk270             : in std_logic;
      write_en_val       : in std_logic;    --Transmit enable
      reset              : in std_logic); 
 --attribute xc_props of ddr_dq_inout : signal is "IOB=TRUE";       
end s3_ddr_iob;
 
architecture arc_s3_ddr_iob of s3_ddr_iob is
 
 
 
 
component FDDRRSE 
port( Q  : out std_logic;
      C0 : in std_logic;
      C1 : in std_logic;
      CE : in std_logic;
      D0 : in std_logic;
      D1 : in std_logic;
      R  : in std_logic;
      S  : in std_logic);
end component;
 
component FDCE 
port(
       D   : in std_logic; 
       CLR : in std_logic; 
       C   : in std_logic; 
       Q   : out std_logic; 
       CE  : in std_logic);
end component;
 
component OBUFT
port (
       I : in std_logic;
       T : in std_logic;
       O : out std_logic);
end component;
 
component IBUF
port (
       I : in std_logic;
       O : out std_logic);
end component;
 
component FDRE
port(
       D  : in std_logic;
       R  : in std_logic; 
       C  : in std_logic; 
       Q  : out std_logic; 
       CE : in std_logic);
end component;
 
 
--***********************************************************************\
--     Internal signal declaration
--***********************************************************************/
 
signal ddr_en       : std_logic;  -- Tri-state enable signal
signal ddr_dq_q     : std_logic;  -- Data output intermediate signal
--signal ddr_dq_o     : std_logic;  -- Data output intermediate signal
signal GND          : std_logic;
signal clock_en     : std_logic := '1';
signal enable_b     : std_logic;
 
signal ddr_dq_ibuf  : std_logic;
signal clk_rx_rise  : std_logic;
signal clk_rx_fall  : std_logic;
 
 
begin
 
--PL: om van een warning af te komen... doet hetzelfde als de default waarde
clock_en <= '1';
--
GND    <= '0';
enable_b <= not write_en_val;
 
-- Transmission data path
 
 
DDR_OUT : FDDRRSE port map
            (Q  => ddr_dq_q, 
             C0 => clk270, 
             C1 => clk90, 
             CE => clock_en,
             D0 => write_data_rising, 
             D1 => write_data_falling, 
             R  => GND, 
             S  => GND);
 
DQ_T   :   FDCE port map
           ( D   => enable_b, 
             CLR => reset, 
             C   => clk270, 
             Q   => ddr_en, 
             CE  => clock_en);
 
 
DQ_OBUFT : OBUFT port map
             ( I => ddr_dq_q,
               T => ddr_en,
               O => ddr_dq_inout);
 
-- Receive data path
 
--old DQ_IBUF :  IBUF port map
--old              ( I => ddr_dq_inout,
--old                O => read_data_in);
 
 
 
 
-- Receive data path
 
 
clk_rx_rise  <=      clk_rx ;
clk_rx_fall  <=  not clk_rx ;
 
 
DQ_IBUF :  IBUF port map
             ( I => ddr_dq_inout,
               O => ddr_dq_ibuf);
 
-- Clock data in
DQ_RISE : FDRE port map
           ( D  => ddr_dq_ibuf, 
             R  => GND, 
             C  => clk_rx_rise,  
             Q  => read_data_in_rising, 
             CE => read_dq_ce); 
 
DQ_FALL : FDRE port map
           ( D  => ddr_dq_ibuf, 
             R  => GND, 
             C  => clk_rx_fall, 
             Q  => read_data_in_falling, 
             CE => read_dq_ce); 
 
 
 
 end arc_s3_ddr_iob;