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[/] [pulse_processing_algorithm/] [top.vhd] - Rev 2
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-- ***************************************************************************************** -- * top.vhd * -- * SIS3302 ADC FPGA * -- ***************************************************************************************** -- * date: 02.05.2005 * -- ***************************************************************************************** -- * * -- * Version 33021405 PSA * -- * last modification: 02.09.2009 * -- * ADC FPGA: - * -- * - * -- * * -- ***************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity top is port( system_clk_p : in std_logic := '0'; system_clk_n : in std_logic := '0'; system_adc_clk_p : in std_logic := '0'; system_adc_clk_n : in std_logic := '0'; adc1_clk_out_p : OUT std_logic := '0'; adc1_clk_out_n : OUT std_logic := '0'; adc2_clk_out_p : OUT std_logic := '0'; adc2_clk_out_n : OUT std_logic := '0'; adc1_dco_p : in std_logic := '0'; adc1_dco_n : in std_logic := '0'; adc1_din_p : in std_logic_vector(15 downto 0); adc1_din_n : in std_logic_vector(15 downto 0); adc2_dco_p : in std_logic := '0'; adc2_dco_n : in std_logic := '0'; adc2_din_p : in std_logic_vector(15 downto 0); adc2_din_n : in std_logic_vector(15 downto 0); -- VME-ADC FPGA Interface i_fpga_reset_l : in std_logic ; -- -- FPGA_PROT_0 ; für clock und ddr logic i_fpga_key_reset_l : in std_logic ; -- FPGA_PROT_9 i_fpga_sel_l : in std_logic ; i_fpga_write_l : in std_logic ; i_fpga_block_l : in std_logic ; i_fpga_ds_l : in std_logic ; wst_out_l_oreg : OUT std_logic := '0'; io_fpga_ad: inout std_logic_VECTOR(31 downto 0); FPGA_ADC_B1_SAMPLE_ENABLED_L: in STD_LOGIC ; -- FPGA_PROT_5 = start_buffer(0) FPGA_ADC_B2_SAMPLE_ENABLED_L: in STD_LOGIC ; -- FPGA_PROT_6 = start_buffer(1) FPGA_ADC_SAMPLE_START_L: in STD_LOGIC ; -- FPGA_PROT_7 = externaltrigger = trigger_pulse FPGA_ADC_SAMPLE_STOP_L: in STD_LOGIC ; -- FPGA_PROT_8 = ext_lemo_in3_ifd_l FPGA_ADC_PROT13_L: in STD_LOGIC ; -- FPGA_prot13 = ext_lemo_in2_ifd_l FPGA_ADC_PROT14_L: in STD_LOGIC ; -- FPGA_prot14 = ext_lemo_in1_ifd_l FPGA_LEMO_USER_IN_L: in STD_LOGIC ; -- FPGA_PROT_10 = stop_events FPGA_ADC_TIMESTAMP_CLR_L:in STD_LOGIC ; -- FPGA_PROT_11 FPGA_ADC_SAMPLE_LOGIC_RESET_L: in STD_LOGIC ; -- FPGA_PROT_12 FPGA_ADC_LED_TIMESTAMP_OVERFLOW_PULSE_L: out STD_LOGIC ; -- FPGA_PROT_15 FPGA_ADC1_TRIGGER_L: out STD_LOGIC ; -- FPGA1_SEL1 FPGA_ADC2_TRIGGER_L: out STD_LOGIC ; -- FPGA1_SEL2 FPGA_ADC12_BUSY_L: out STD_LOGIC ; -- FPGA1_SEL3 FPGA_ADC12_EVENT_END_L: out STD_LOGIC ; -- FPGA1_SEL4 CON_WITH_ADC12_OUT1_L: out std_logic := '0'; -- not used CON_WITH_ADC12_IN1_L: in std_logic := '0'; -- enable_externaltrigger signal cascade from neighbour CON_WITH_ADC12_OUT2_L: out std_logic := '0'; -- not used CON_WITH_ADC12_IN2_L: in std_logic := '0'; -- alleventsdone signal cascade from neighbour CON_WITH_ADC78_IN1_L: in std_logic := '0'; -- not used CON_WITH_ADC78_OUT1_L: out std_logic := '0'; -- enable_externaltrigger signal cascade to neighbour CON_WITH_ADC78_IN2_L: in std_logic := '0'; -- not used CON_WITH_ADC78_OUT2_L: out std_logic := '0'; -- alleventsdone signal cascade to neighbour ddr1_clk : out std_logic ; ddr1_clkb : out std_logic := '0'; ddr1_dqs_reserve : OUT std_logic_vector(1 downto 0); ddr1_ba2_reserve : OUT std_logic := '0'; ddr1_rst_dqs_div_iob : INOUT std_logic ; ddr1_dqs : INOUT std_logic_vector(1 downto 0):= (others => 'Z'); ddr1_dq : INOUT std_logic_vector(15 downto 0):= (others => 'Z'); ddr1_dm : OUT std_logic_vector(1 downto 0); ddr1_ba : OUT std_logic_vector(1 downto 0); ddr1_address : OUT std_logic_vector(15 downto 0); ddr1_rasb : OUT std_logic := '0'; ddr1_casb : OUT std_logic := '0'; ddr1_web : OUT std_logic := '0'; ddr1_cke : OUT std_logic := '0'; ddr1_csb : OUT std_logic ; ddr1_ODT0 : OUT std_logic ; ddr2_clk : out std_logic ; ddr2_clkb : out std_logic ; ddr2_dqs_reserve : OUT std_logic_vector(1 downto 0); ddr2_ba2_reserve : OUT std_logic := '0'; ddr2_dqs : INOUT std_logic_vector(1 downto 0):= (others => 'Z'); ddr2_dq : INOUT std_logic_vector(15 downto 0):= (others => 'Z'); ddr2_dm : OUT std_logic_vector(1 downto 0); ddr2_ba : OUT std_logic_vector(1 downto 0); ddr2_address : OUT std_logic_vector(15 downto 0); ddr2_rasb : OUT std_logic := '0'; ddr2_casb : OUT std_logic := '0'; ddr2_web : OUT std_logic := '0'; ddr2_cke : OUT std_logic := '0'; ddr2_csb : OUT std_logic := '0'; ddr2_ODT0 : OUT std_logic := '0'; ddr2_rst_dqs_div_iob : INOUT std_logic := '0'; FPGA_ID_D0 : IN std_logic := '0'; FPGA_ID_D1 : IN std_logic ); end top; architecture Behavioral of top is Function to_std_logic(X: in Boolean) return Std_Logic is variable ret : std_logic := '0'; begin if x then ret := '1'; else ret := '0'; end if; return ret; end to_std_logic; signal i_system_clk : std_logic := '0'; signal system_clk_ibufg : std_logic := '0'; signal sys_clk_100 : std_logic := '0'; signal clk_int : std_logic := '0'; signal clk180_int : std_logic := '0'; signal clk90_int : std_logic := '0'; signal clk270_int : std_logic := '0'; signal clk_int_dcm_lock : std_logic := '0'; --signal sys_clk_div2 : std_logic := '0'; --peter signal ddr2_clk_system_reset : std_logic := '0'; signal ddr2_clk_system_reset_cnt : std_logic_VECTOR(5 downto 0); signal i_system_adc_clk : std_logic := '0'; signal system_adc_clk : std_logic := '0'; signal fpga_sel_ireg : std_logic := '0'; signal fpga_ds_ireg : std_logic := '0'; signal fpga_write_ireg : std_logic := '0'; signal fpga_block_ireg : std_logic := '0'; signal fpga_reset_ibuf : std_logic := '0'; signal fpga_key_reset_ibuf : std_logic := '0'; signal fpga_key_reset_delay1 : std_logic := '0'; signal fpga_key_reset_delay2 : std_logic := '0'; signal fpga_key_reset_degliched : std_logic := '0'; signal vme_out_ad_en : std_logic := '0'; signal vme_ad_oreg : std_logic_VECTOR (31 downto 0); signal vme_ad_ireg : std_logic_VECTOR (31 downto 0); signal wst_out_en : std_logic := '0'; signal vme_out_wst : std_logic := '0'; signal adc1_dco_clk : std_logic := '0'; signal adc1_clk_l : std_logic := '0'; signal adc1_clk : std_logic := '0'; signal adc1_buf_din : std_logic_vector(15 downto 0); signal adc1_din : std_logic_vector(15 downto 0); signal adc1_ram_fifo_data_wr_data : std_logic_VECTOR(31 downto 0); signal adc1_ram_fifo_data_wr_ce : std_logic := '0'; signal adc1_ram_fifo_addr_wr_ce : std_logic := '0'; signal adc1_ram_fifo_addr_wr_addr : std_logic_VECTOR(31 downto 0); signal adc1_last_buffer_adc_ram_fifo_wr_addr : std_logic_VECTOR(31 downto 0); signal adc2_dco_clk : std_logic := '0'; signal adc2_clk_l : std_logic := '0'; signal adc2_clk : std_logic := '0'; signal adc2_buf_din : std_logic_vector(15 downto 0); signal adc2_din : std_logic_vector(15 downto 0); signal adc2_ram_fifo_data_wr_data : std_logic_VECTOR(31 downto 0); signal adc2_ram_fifo_data_wr_ce : std_logic := '0'; signal adc2_ram_fifo_addr_wr_ce : std_logic := '0'; signal adc2_ram_fifo_addr_wr_addr : std_logic_VECTOR(31 downto 0); signal adc2_last_buffer_adc_ram_fifo_wr_addr : std_logic_VECTOR(31 downto 0); signal vme_0x20_reg_S : std_logic_vector(31 downto 0); signal vme_b1_addr_ld : std_logic := '0'; signal vme_b2_addr_ld : std_logic := '0'; signal rst : std_logic := '1'; signal ram1_vme_wr_addr_fifo_q : std_logic_VECTOR(31 downto 0); signal ram1_fifo_pipe_wr_count : std_logic_VECTOR(8 downto 0); signal ram1_vme_wr_addr_fifo_pipe_rd_en : std_logic := '0'; signal ram1_vme_wr_addr_fifo_pipe_valid : std_logic := '0'; signal ram1_wr_bank_row_last_addr_flag : std_logic := '0'; signal ram1_wr_bank_row_addr_conflict_flag : std_logic := '0'; signal ram1_wr_addr_fifo_pipe_burst_valid : std_logic := '0'; signal ram1_vme_wr_fifo_rd_en : std_logic := '0'; signal ram1_vme_rd_addr_fifo_d : std_logic_VECTOR(31 downto 0); signal ram1_vme_rd_addr_fifo_q : std_logic_VECTOR(31 downto 0); signal ram1_vme_rd_addr_wr_fifo_pipe_empty : std_logic := '0'; -- new 14.08.2009 signal ram1_vme_rd_addr_fifo_pipe_wr_count : std_logic_VECTOR(8 downto 0); signal ram1_vme_rd_data_fifo_pipe_rd_count : std_logic_VECTOR(8 downto 0); signal ram1_vme_rd_data_fifo_aint : std_logic := '0'; signal ram1_vme_rd_addr_fifo_clr : std_logic := '0'; signal ram1_vme_rd_addr_fifo_wr_en : std_logic := '0'; signal ram1_read_vme_address_fifo_pipe_asynch_reset: std_logic := '0'; signal ram1_vme_rd_addr_fifo_pipe_rd_en : std_logic := '0'; signal ram1_vme_rd_bank_row_last_addr_flag : std_logic := '0'; signal ram1_vme_rd_bank_row_addr_conflict_flag: std_logic := '0'; signal ram1_vme_rd_addr_fifo_pipe_burst_valid: std_logic := '0'; signal ram1_vme_rd_addr_fifo_pipe_valid: std_logic := '0'; signal ram1_rd_addr_mux_en: std_logic := '0'; signal ram1_vme_rd_fifo_rd_en: std_logic := '0'; signal ram1_rd_data_fifo_empty: std_logic := '0'; signal ram1_rd_data_fifo_q: std_logic_VECTOR(31 downto 0); signal ram1_ddr2_user_output_data: std_logic_VECTOR(31 downto 0); signal ram1_ddr2_user_data_val: std_logic := '0'; signal ram1_ddr2_user_input_data: std_logic_VECTOR(31 downto 0); signal ram1_ddr2_command_register: std_logic_VECTOR(3 downto 0); -- input signal ram1_ddr2_controller_address: std_logic_VECTOR(24 downto 0); -- input signal ram1_ddr2_burst_done: std_logic := '0'; -- input signal ram1_ddr2_cmd_ack: std_logic := '0'; -- output signal ram1_ddr2_autorefresh_done: std_logic := '0'; -- output signal ram1_ddr2_init_done: std_logic := '0'; -- output signal ram1_ddr2_rst_calib1: std_logic := '0'; signal ram1_ddr2_delay_sel: std_logic_VECTOR(4 downto 0); signal ram1_ddr2_rasb_cntrl: std_logic := '0'; signal ram1_ddr2_casb_cntrl: std_logic := '0'; signal ram1_ddr2_web_cntrl: std_logic := '0'; signal ram1_ddr2_cke_cntrl: std_logic := '0'; signal ram1_ddr2_csb_cntrl: std_logic := '0'; signal ram1_ddr2_ODT_cntrl: std_logic := '0'; signal ram1_ddr2_ba_cntrl: std_logic_VECTOR(1 downto 0); signal ram1_ddr2_address_cntrl: std_logic_VECTOR(12 downto 0); signal ram1_ddr2_dqs_reset: std_logic := '0'; signal ram1_ddr2_dqs_enable: std_logic := '0'; signal ram1_ddr2_write_enable: std_logic := '0'; signal ram1_ddr2_rst_dqs_div_int: std_logic := '0'; signal ram1_ddr2_rst_dqs_div: std_logic := '0'; signal ram1_ddr2_sys_rst: std_logic := '0'; signal ram1_ddr2_sys_rst90: std_logic := '0'; signal ram1_ddr2_sys_rst180: std_logic := '0'; signal ram1_ddr2_sys_rst180_orig: std_logic := '0'; signal ram1_ddr2_sys_rst270: std_logic := '0'; signal ram1_ddr2_dqs_int_delay_in0: std_logic := '0'; signal ram1_ddr2_dqs_int_delay_in1: std_logic := '0'; signal ram1_ddr2_data_mask_f: std_logic_VECTOR(1 downto 0); signal ram1_ddr2_data_mask_r: std_logic_VECTOR(1 downto 0); signal ram1_ddr2_write_data_falling: std_logic_VECTOR(15 downto 0); signal ram1_ddr2_write_data_rising: std_logic_VECTOR(15 downto 0); signal ram1_ddr2_dq_in_rising: std_logic_VECTOR(15 downto 0); signal ram1_ddr2_dq_in_falling: std_logic_VECTOR(15 downto 0); signal ram1_ddr2_write_en_val: std_logic := '0'; signal ram1_ddr2_write_en_val1: std_logic := '0'; signal ram1_ddr2_reset90_r: std_logic := '0'; signal ram2_vme_wr_addr_fifo_q: std_logic_VECTOR(31 downto 0); signal ram2_fifo_pipe_wr_count: std_logic_VECTOR(8 downto 0); signal ram2_vme_wr_addr_fifo_pipe_rd_en: std_logic := '0'; signal ram2_vme_wr_addr_fifo_pipe_valid: std_logic := '0'; signal ram2_wr_bank_row_last_addr_flag: std_logic := '0'; signal ram2_wr_bank_row_addr_conflict_flag: std_logic := '0'; signal ram2_wr_addr_fifo_pipe_burst_valid: std_logic := '0'; signal ram2_vme_wr_fifo_rd_en: std_logic := '0'; signal ram2_vme_rd_addr_fifo_d: std_logic_VECTOR(31 downto 0); signal ram2_vme_rd_addr_fifo_q: std_logic_VECTOR(31 downto 0); signal ram2_vme_rd_addr_wr_fifo_pipe_empty: std_logic := '0'; -- new 14.08.2009 signal ram2_vme_rd_addr_fifo_pipe_wr_count: std_logic_VECTOR(8 downto 0); signal ram2_vme_rd_data_fifo_pipe_rd_count: std_logic_VECTOR(8 downto 0); signal ram2_vme_rd_data_fifo_aint: std_logic := '0'; signal ram2_vme_rd_addr_fifo_clr: std_logic := '0'; signal ram2_vme_rd_addr_fifo_wr_en: std_logic := '0'; signal ram2_read_vme_address_fifo_pipe_asynch_reset: std_logic := '0'; signal ram2_vme_rd_addr_fifo_pipe_rd_en: std_logic := '0'; signal ram2_vme_rd_bank_row_last_addr_flag: std_logic := '0'; signal ram2_vme_rd_bank_row_addr_conflict_flag: std_logic := '0'; signal ram2_vme_rd_addr_fifo_pipe_burst_valid: std_logic := '0'; signal ram2_vme_rd_addr_fifo_pipe_valid: std_logic := '0'; signal ram2_rd_addr_mux_en: std_logic := '0'; signal ram2_vme_rd_fifo_rd_en: std_logic := '0'; signal ram2_rd_data_fifo_empty: std_logic := '0'; signal ram2_rd_data_fifo_q: std_logic_VECTOR(31 downto 0); signal ram2_ddr2_controller_address: std_logic_VECTOR(24 downto 0); -- input signal ram2_ddr2_command_register: std_logic_VECTOR(3 downto 0); -- input signal ram2_ddr2_burst_done: std_logic := '0'; -- input signal ram2_ddr2_cmd_ack: std_logic := '0'; -- output signal ram2_ddr2_autorefresh_done: std_logic := '0'; -- output signal ram2_ddr2_init_done: std_logic := '0'; -- output signal ram2_ddr2_user_input_data: std_logic_VECTOR(31 downto 0); signal ram2_ddr2_user_output_data: std_logic_VECTOR(31 downto 0); signal ram2_ddr2_user_data_val: std_logic := '0'; signal ddr_config_register1: std_logic_VECTOR(14 downto 0); signal ddr_config_register2: std_logic_VECTOR(12 downto 0); signal ramx_ddr2_delay_sel: std_logic_VECTOR(4 downto 0); signal ram2_ddr2_sys_rst: std_logic := '0'; signal ram2_ddr2_sys_rst90: std_logic := '0'; signal ram2_ddr2_sys_rst180: std_logic := '0'; signal ram2_ddr2_sys_rst180_orig: std_logic := '0'; signal ram2_ddr2_sys_rst270: std_logic := '0'; signal ram2_ddr2_delay_sel: std_logic_VECTOR(4 downto 0); signal ram2_ddr2_rst_calib1: std_logic := '0'; signal ram2_ddr2_rst_dqs_div: std_logic := '0'; signal ram2_ddr2_write_enable: std_logic := '0'; signal ram2_ddr2_rst_dqs_div_int: std_logic := '0'; signal ram2_ddr2_dqs_enable: std_logic := '0'; signal ram2_ddr2_write_en_val : std_logic := '0'; signal ram2_ddr2_write_en_val1 : std_logic := '0'; signal ram2_ddr2_reset90_r : std_logic := '0'; signal ram2_ddr2_dqs_int_delay_in0 : std_logic := '0'; signal ram2_ddr2_dqs_int_delay_in1 : std_logic := '0'; signal ram2_ddr2_data_mask_f : std_logic_VECTOR(1 downto 0); signal ram2_ddr2_data_mask_r : std_logic_VECTOR(1 downto 0); signal ram2_ddr2_write_data_falling : std_logic_VECTOR(15 downto 0); signal ram2_ddr2_write_data_rising : std_logic_VECTOR(15 downto 0); signal ram2_ddr2_dq_in_rising : std_logic_VECTOR(15 downto 0); signal ram2_ddr2_dq_in_falling : std_logic_VECTOR(15 downto 0); signal ram2_ddr2_rasb_cntrl : std_logic := '0'; signal ram2_ddr2_casb_cntrl : std_logic := '0'; signal ram2_ddr2_web_cntrl : std_logic := '0'; signal ram2_ddr2_cke_cntrl : std_logic := '0'; signal ram2_ddr2_csb_cntrl : std_logic := '0'; signal ram2_ddr2_ODT_cntrl : std_logic := '0'; signal ram2_ddr2_ba_cntrl : std_logic_VECTOR(1 downto 0); signal ram2_ddr2_address_cntrl : std_logic_VECTOR(12 downto 0); signal ram2_ddr2_dqs_reset : std_logic := '0'; signal ch1_vme_test_write_ram_addr_fifo_ce : std_logic := '0'; signal ch1_vme_test_write_ram_addr_fifo_din : std_logic_VECTOR(31 downto 0); signal ch1_vme_test_write_ram_data_fifo_ce : std_logic := '0'; signal ch1_vme_test_write_ram_data_fifo_din : std_logic_VECTOR(31 downto 0); signal mux_adc1_ram_fifo_addr_wr_ce : std_logic := '0'; signal mux_adc1_ram_fifo_addr_wr_addr : std_logic_VECTOR(31 downto 0); signal mux_adc1_ram_fifo_data_wr_ce : std_logic := '0'; signal mux_adc1_ram_fifo_data_wr_data : std_logic_VECTOR(31 downto 0); signal ch2_vme_test_write_ram_addr_fifo_ce : std_logic := '0'; signal ch2_vme_test_write_ram_addr_fifo_din : std_logic_VECTOR(31 downto 0); signal ch2_vme_test_write_ram_data_fifo_ce : std_logic := '0'; signal ch2_vme_test_write_ram_data_fifo_din : std_logic_VECTOR(31 downto 0); signal mux_adc2_ram_fifo_addr_wr_ce : std_logic := '0'; signal mux_adc2_ram_fifo_addr_wr_addr : std_logic_VECTOR(31 downto 0); signal mux_adc2_ram_fifo_data_wr_ce : std_logic := '0'; signal mux_adc2_ram_fifo_data_wr_data : std_logic_VECTOR(31 downto 0); signal vme_ram1_wr_cycle : std_logic := '0'; signal vme_ram2_wr_cycle : std_logic := '0'; signal vme_ram1_wr_cmd_pulse : std_logic := '0'; signal vme_ram2_wr_cmd_pulse : std_logic := '0'; signal vme_b1_rd : std_logic := '0'; signal vme_b2_rd : std_logic := '0'; signal ramx_vme_bx_rd_cycle : std_logic := '0'; signal ramx_vme_bx_rd_request : std_logic := '0'; signal ramx_vme_bx_rd_dma : std_logic := '0'; signal vme_event_config_reg_S : std_logic_VECTOR(31 downto 0) := (others => '0'); signal vme_0x04_reg_S : std_logic_VECTOR(23 downto 2) := (others => '0'); signal vme_0x30_reg_S : std_logic_VECTOR(31 downto 0) := (others => '0'); signal vme_0x34_reg_S : std_logic_VECTOR(26 downto 0) := (others => '0'); signal vme_0x38_reg_S : std_logic_VECTOR(31 downto 0) := (others => '0'); signal vme_0x3C_reg_S : std_logic_VECTOR(26 downto 0) := (others => '0'); signal vme_adc1_ram_address_counter : std_logic_VECTOR(24 downto 0) := (others => '0'); signal vme_adc2_ram_address_counter : std_logic_VECTOR(24 downto 0) := (others => '0'); signal temp_24: std_logic_VECTOR(31 downto 0); signal temp_28: std_logic_VECTOR(31 downto 0); signal ram1_ddr2_wr_data_wr_count: std_logic_VECTOR(9 downto 0); signal ram2_ddr2_wr_data_wr_count: std_logic_VECTOR(9 downto 0); signal ram1_test_fifo_wr_addr: std_logic_VECTOR(15 downto 0); signal ram2_test_fifo_wr_addr: std_logic_VECTOR(15 downto 0); signal ram1_ddr2_wr_data_rd_count: std_logic_VECTOR(9 downto 0); signal ram1_ddr2_wr_data_rd_empty: std_logic := '0'; signal adc1_clk_fpga_sel_ireg: std_logic := '0'; signal adc2_clk_fpga_sel_ireg: std_logic := '0'; --signal adc1_sample_event_busy: std_logic := '0'; --signal adc2_sample_event_busy: std_logic := '0'; signal adc12_event_logic_busy: std_logic := '0'; signal start_delay1 : std_logic := '0'; signal start_delay2 : std_logic := '0'; signal start_delay3 : std_logic := '0'; signal start_delay4 : std_logic := '0'; signal start_delay5 : std_logic := '0'; signal start_delay6 : std_logic := '0'; signal start_delay7 : std_logic := '0'; signal start_delay8 : std_logic := '0'; signal start_delay9 : std_logic := '0'; signal start_delay10 : std_logic := '0'; signal fpga_reset_delay : std_logic := '0'; signal new_fpga_reset_ibuf : std_logic := '0'; signal adc_sample_logic_reset_l : std_logic := '0'; signal adc_sample_logic_reset : std_logic := '0'; signal vme_0x08_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x0C_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x40_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x44_reg_S : std_logic_vector(15 downto 0) := (others => '0'); signal vme_0x48_reg_S : std_logic_vector(15 downto 0) := (others => '0'); signal vme_0x4C_reg_S : std_logic_vector(15 downto 0) := (others => '0'); signal vme_0x50_reg_S : std_logic_vector(15 downto 0) := (others => '0'); signal vme_0x54_reg_S : std_logic_vector(15 downto 0) := (others => '0'); signal vme_0x58_reg_S : std_logic_vector(15 downto 0) := (others => '0'); signal vme_0x5C_reg_S : std_logic_vector(15 downto 0) := (others => '0'); signal vme_0x60_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x64_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x68_reg_S : std_logic_vector(7 downto 0) := (others => '0'); signal vme_0x80_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x84_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x88_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x8C_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x90_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x94_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x98_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal vme_0x9C_feedback_reg_S : std_logic_vector(31 downto 0) := (others => '0'); signal decay_correction_S : std_logic_vector(31 downto 0) := (others => '0'); signal reshape_correction_S : std_logic_vector(31 downto 0) := (others => '0'); signal buffer_size_S : std_logic_vector(31 downto 0) := (others => '0'); signal int_signal_threshold_S : STD_LOGIC_VECTOR(15 downto 0) := conv_std_logic_vector(1024,16); -- default value of 1024 decimal signal mwd_pwr_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(5, 8); -- original default value signal cf_pwr_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(4, 8); -- original default value = (mwd_power - 1) signal cf_integral_pwr_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(4, 8); -- original default value signal baseline_pwr_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(9, 10); -- original default value signal baseline_inhibit_cnt_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value signal event_inhibit_cnt_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(16, 8); -- original default value signal FE1_running_S : std_logic := '0'; signal FE2_running_S : std_logic := '0'; signal FE1_enable_S : std_logic := '0'; signal FE2_enable_S : std_logic := '0'; signal cmd_invert_data_in_S : std_logic := '0'; signal feedback_bus0_S : std_logic_vector(31 downto 0) := (others => '0'); signal feedback_bus1_S : std_logic_vector(31 downto 0) := (others => '0'); signal feedback_bus2_S : std_logic_vector(31 downto 0) := (others => '0'); signal feedback_bus3_S : std_logic_vector(31 downto 0) := (others => '0'); signal feedback_bus4_S : std_logic_vector(31 downto 0) := (others => '0'); signal feedback_bus5_S : std_logic_vector(31 downto 0) := (others => '0'); signal feedback_bus6_S : std_logic_vector(31 downto 0) := (others => '0'); signal mca_ram1_rd_req : std_logic := '0'; signal mca_ram1_rd_addr : std_logic_VECTOR(24 downto 0); signal mca_ram1_rd_gt : std_logic := '0'; signal mca_ram1_rd_data_valid : std_logic := '0'; signal mca_ram1_rd_data_ld1 : std_logic := '0'; signal mca_ram1_rd_data_ld2 : std_logic := '0'; signal mca_ram1_rd_data_fifo_first_word : std_logic_VECTOR(31 downto 0); signal mca_ram1_rd_data_fifo_second_word : std_logic_VECTOR(31 downto 0); signal mca_ram2_rd_req : std_logic := '0'; signal mca_ram2_rd_addr : std_logic_VECTOR(24 downto 0); signal mca_ram2_rd_gt : std_logic := '0'; signal mca_ram2_rd_data_valid : std_logic := '0'; signal mca_ram2_rd_data_ld1 : std_logic := '0'; signal mca_ram2_rd_data_ld2 : std_logic := '0'; signal mca_ram2_rd_data_fifo_first_word : std_logic_VECTOR(31 downto 0); signal mca_ram2_rd_data_fifo_second_word : std_logic_VECTOR(31 downto 0); signal ram1_vme_rd_data_fifo_empty : std_logic := '0'; signal ram2_vme_rd_data_fifo_empty : std_logic := '0'; signal ram1_rd_fifo_rd_en : std_logic := '0'; signal ram2_rd_fifo_rd_en : std_logic := '0'; signal adc1_ram_fifo_data_full : std_logic := '0'; signal adc2_ram_fifo_data_full : std_logic := '0'; component BUFG port ( I : in std_logic := '0'; O : out std_logic); end component; component IBUFG port ( I : in std_logic := '0'; O : out std_logic); end component; component IBUF port ( I : in std_logic := '0'; O : out std_logic); end component; COMPONENT sys_clk_dcm PORT( sys_clk_in : IN std_logic := '0'; rst : IN std_logic := '0'; sys_clk_out : OUT std_logic := '0'; sys_clkfx_out : OUT std_logic := '0'; dcm_sys_clock_locked : OUT std_logic := '0'; sys_clk_div2 : out std_logic ); END COMPONENT; COMPONENT ddr_clk_dcm PORT( sys_clk : IN std_logic := '0'; rst : IN std_logic := '0'; clk_int : OUT std_logic := '0'; clk180_int : OUT std_logic := '0'; clk90_int : OUT std_logic := '0'; clk270_int : OUT std_logic := '0'; dcm_lock : OUT std_logic := '0'; ddr1_clk : OUT std_logic := '0'; ddr1_clkb : OUT std_logic := '0'; ddr2_clk : OUT std_logic := '0'; ddr2_clkb : OUT std_logic ); END COMPONENT; component IBUFDS is port ( I : in STD_LOGIC; IB : in STD_LOGIC; O : out STD_LOGIC ); end component; component IBUFGDS is port( I : in STD_LOGIC; IB : in STD_LOGIC; O : out STD_LOGIC ); end component; component OBUFDS is port ( I : in STD_LOGIC; O : out STD_LOGIC; OB : out STD_LOGIC ); end component; component OBUFT port( I : in std_logic := '0'; T : in std_logic := '0'; O : out std_logic); end component; COMPONENT FD PORT( C : IN std_logic := '0'; D : IN std_logic := '0'; Q : OUT std_logic ); END COMPONENT; component OFD port( Q : out STD_LOGIC; D : in STD_LOGIC; C : in STD_LOGIC); end component ; component IFD is port ( C : in STD_LOGIC; D : in STD_LOGIC; Q : out STD_LOGIC ); end component; component Feature_Extraction port( uP_CLK : in std_logic; Reset : in std_logic; ADC_CLK : in std_logic; ADCin : in std_logic_vector(15 downto 0); invert_data_in : in std_logic; externaltrigger : in std_logic; softwaretrigger : in std_logic; cmd_output_select : in std_logic_vector(3 downto 0); cmd_start_adc : in std_logic; cmd_enableFE : in std_logic; cmd_baseline_enable : in std_logic; cmd_double_CF : in std_logic; cmd_program_params : in std_logic; cmd_bypass_mwd : in std_logic; cmd_bypass_reshape : in std_logic; decay_correction_in : in STD_LOGIC_VECTOR(31 downto 0); reshape_correction_in : in STD_LOGIC_VECTOR(31 downto 0); buffer_size : in std_logic_vector(31 downto 0); -- number of samples to read from buffer int_signal_threshold_in : in std_logic_vector(15 downto 0); -- event-trigger threshold on the integrated input signal mwd_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for mwd size cf_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for cf delay cf_integral_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for cf-generation baseline_pwr_in : in STD_LOGIC_VECTOR(7 downto 0); baseline_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- baseline data-collect inhibition after event event_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- event detect inhibition after event fb_flowctrl_running : out std_logic := '0'; fb_chain_enable : out std_logic := '0'; feedback_port0 : out std_logic_vector(31 downto 0); feedback_port1 : out std_logic_vector(31 downto 0); feedback_port2 : out std_logic_vector(15 downto 0); feedback_port3 : out std_logic_vector(31 downto 0); adc_ram_fifo_data_wr_data : out std_logic_vector(31 downto 0); adc_ram_fifo_address : out std_logic_vector(31 downto 0); adc_ram_fifo_data_wr_ce : out std_logic := '0'; adc_ram_fifo_addr_wr_ce : out std_logic := '0'; last_buffer_adc_ram_fifo_wr_addr : out std_logic_vector(31 downto 0) ); end component; component blk_asy_fifo_1023x16 port(din: IN std_logic_VECTOR(15 downto 0); wr_en: IN std_logic := '0'; wr_clk: IN std_logic := '0'; rd_en: IN std_logic := '0'; rd_clk: IN std_logic := '0'; ainit: IN std_logic := '0'; dout: OUT std_logic_VECTOR(15 downto 0); full: OUT std_logic := '0'; empty: OUT std_logic := '0'; wr_count: OUT std_logic_VECTOR(9 downto 0); rd_count: OUT std_logic_VECTOR(9 downto 0) ); end component; component blk_asy_fifo_511x32 port ( din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic := '0'; wr_clk: IN std_logic := '0'; rd_en: IN std_logic := '0'; rd_clk: IN std_logic := '0'; ainit: IN std_logic := '0'; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic := '0'; empty: OUT std_logic := '0'; wr_count: OUT std_logic_VECTOR(8 downto 0); rd_count: OUT std_logic_VECTOR(8 downto 0)); end component; COMPONENT ram_address_fifo_pipe PORT( clk_wr : IN std_logic := '0'; clk180 : IN std_logic := '0'; asynch_reset : IN std_logic := '0'; fifo_input_d : IN std_logic_vector(31 downto 0); fifo_input_wr_en : IN std_logic := '0'; fifo_pipe_rd_en : IN std_logic := '0'; sy_clk_wr_fifo_pipe_empty : OUT std_logic := '0'; bank_row_last_addr_flag : OUT std_logic := '0'; bank_row_addr_conflict_flag : OUT std_logic := '0'; fifo_pipe_burst_valid : OUT std_logic := '0'; fifo_pipe_valid : OUT std_logic := '0'; fifo_pipe_out_reg : OUT std_logic_vector(31 downto 0); fifo_pipe_wr_count : OUT std_logic_vector(8 downto 0) ); END COMPONENT; COMPONENT cal_top PORT( clk0 : IN std_logic := '0'; reset : IN std_logic := '0'; flop2 : OUT std_logic_vector(31 downto 0); tapForDqs : OUT std_logic_vector(4 downto 0) ); END COMPONENT; COMPONENT infrastructure PORT( reset_in : IN std_logic := '0'; clk_int : IN std_logic := '0'; clk180_int : IN std_logic := '0'; clk90_int : IN std_logic := '0'; dcm_lock : IN std_logic := '0'; rst_calib1 : IN std_logic := '0'; ramx_ddr2_delay_sel_val : IN std_logic_vector(4 downto 0); delay_sel_val1_val : OUT std_logic_vector(4 downto 0); sys_rst_val : OUT std_logic := '0'; sys_rst90_val : OUT std_logic := '0'; sys_rst180_val : OUT std_logic := '0'; sys_rst270_val : OUT std_logic ); END COMPONENT; COMPONENT ddr2_readwrite_fsm PORT( clk180_int : IN std_logic := '0'; clk_int_dcm_lock : IN std_logic := '0'; rst180 : IN std_logic := '0'; wr_bank_row_last_addr_flag : IN std_logic := '0'; wr_bank_row_addr_conflict_flag : IN std_logic := '0'; wr_addr_fifo_pipe_burst_valid : IN std_logic := '0'; wr_addr_fifo_pipe_valid : IN std_logic := '0'; ram_fifo_pipe_wr_count : IN std_logic_vector(8 downto 0); rd_bank_row_last_addr_flag : IN std_logic := '0'; rd_bank_row_addr_conflict_flag : IN std_logic := '0'; rd_addr_fifo_pipe_burst_valid : IN std_logic := '0'; rd_addr_fifo_pipe_valid : IN std_logic := '0'; ddr2_ctrl_cmd_ack : IN std_logic := '0'; ddr2_ctrl_init : IN std_logic := '0'; ddr2_ctrl_ar_done : IN std_logic := '0'; wr_addr_fifo_pipe_rd_en : OUT std_logic := '0'; wr_data_fifo_rd_en : OUT std_logic := '0'; rd_addr_fifo_pipe_rd_en : OUT std_logic := '0'; rd_addr_mux_en : OUT std_logic := '0'; ddr2_ctrl_command_register : OUT std_logic_vector(3 downto 0); ddr2_ctrl_burst_done : OUT std_logic ); END COMPONENT; COMPONENT controller PORT( clk : IN std_logic := '0'; clk180_int : IN std_logic := '0'; rst0 : IN std_logic := '0'; rst180 : IN std_logic := '0'; address : IN std_logic_vector(22 downto 0); bank_address : IN std_logic_vector(1 downto 0); config_register1 : IN std_logic_vector(14 downto 0); config_register2 : IN std_logic_vector(12 downto 0); command_register : IN std_logic_vector(3 downto 0); burst_done : IN std_logic := '0'; ddr_rasb_cntrl : OUT std_logic := '0'; ddr_casb_cntrl : OUT std_logic := '0'; ddr_web_cntrl : OUT std_logic := '0'; ddr_ba_cntrl : OUT std_logic_vector(1 downto 0); ddr_address_cntrl : OUT std_logic_vector(12 downto 0); ddr_cke_cntrl : OUT std_logic := '0'; ddr_csb_cntrl : OUT std_logic := '0'; ddr_ODT_cntrl : OUT std_logic := '0'; dqs_enable : OUT std_logic := '0'; dqs_reset : OUT std_logic := '0'; write_enable : OUT std_logic := '0'; rst_calib : OUT std_logic := '0'; rst_dqs_div_int : OUT std_logic := '0'; cmd_ack : OUT std_logic := '0'; init : OUT std_logic := '0'; ar_done : OUT std_logic ); END COMPONENT; COMPONENT ddr2_data_path PORT( user_input_data : IN std_logic_vector(31 downto 0); clk : IN std_logic := '0'; clk180 : IN std_logic := '0'; clk90 : IN std_logic := '0'; reset : IN std_logic := '0'; reset90 : IN std_logic := '0'; reset180 : IN std_logic := '0'; reset270 : IN std_logic := '0'; write_enable : IN std_logic := '0'; rst_dqs_div_in : IN std_logic := '0'; delay_sel : IN std_logic_vector(4 downto 0); dqs_int_delay_in0 : IN std_logic := '0'; dqs_int_delay_in1 : IN std_logic := '0'; dq_in_rising : IN std_logic_vector(15 downto 0); dq_in_falling : IN std_logic_vector(15 downto 0); u_data_val : OUT std_logic := '0'; user_output_data : OUT std_logic_vector(31 downto 0); write_en_val : OUT std_logic := '0'; write_en_val1 : OUT std_logic := '0'; reset90_r_val : OUT std_logic := '0'; data_mask_f : OUT std_logic_vector(1 downto 0); data_mask_r : OUT std_logic_vector(1 downto 0); write_data_falling : OUT std_logic_vector(15 downto 0); write_data_rising : OUT std_logic_vector(15 downto 0); test_fifo_wr_addr : OUT std_logic_vector(15 downto 0) ); END COMPONENT; COMPONENT ddr2_iobs PORT( clk0 : IN std_logic := '0'; clk180 : IN std_logic := '0'; clk90 : IN std_logic := '0'; ddr_rasb_cntrl : IN std_logic := '0'; ddr_ODT_cntrl : IN std_logic := '0'; ddr_casb_cntrl : IN std_logic := '0'; ddr_web_cntrl : IN std_logic := '0'; ddr_cke_cntrl : IN std_logic := '0'; ddr_csb_cntrl : IN std_logic := '0'; ddr_address_cntrl : IN std_logic_vector(12 downto 0); ddr_ba_cntrl : IN std_logic_vector(1 downto 0); rst_dqs_div_int : IN std_logic := '0'; dqs_reset : IN std_logic := '0'; dqs_enable : IN std_logic := '0'; write_data_falling : IN std_logic_vector(15 downto 0); write_data_rising : IN std_logic_vector(15 downto 0); write_en_val : IN std_logic := '0'; write_en_val1 : IN std_logic := '0'; reset90_r : IN std_logic := '0'; data_mask_f : IN std_logic_vector(1 downto 0); data_mask_r : IN std_logic_vector(1 downto 0); ddr_dqs : INOUT std_logic_vector(1 downto 0); ddr_dq : INOUT std_logic_vector(15 downto 0); ddr_ODT0 : OUT std_logic := '0'; ddr_rasb : OUT std_logic := '0'; ddr_casb : OUT std_logic := '0'; ddr_web : OUT std_logic := '0'; ddr_ba : OUT std_logic_vector(1 downto 0); ddr_address : OUT std_logic_vector(15 downto 0); ddr_cke : OUT std_logic := '0'; ddr_csb : OUT std_logic := '0'; rst_dqs_div_iob : INOUT std_logic := '0'; rst_dqs_div : OUT std_logic := '0'; dqs_int_delay_in0 : OUT std_logic := '0'; dqs_int_delay_in1 : OUT std_logic := '0'; dq_in_rising : OUT std_logic_vector(15 downto 0); dq_in_falling : OUT std_logic_vector(15 downto 0); ddr_dm : OUT std_logic_vector(1 downto 0) ); END COMPONENT; COMPONENT vme_mca_ram_read_controller PORT( sys_clk_100 : IN std_logic := '0'; reset : IN std_logic := '0'; vme_ad_ireg : IN std_logic_vector(31 downto 0); vme_adcx_addr_ld : IN std_logic := '0'; vme_adcx_rd : IN std_logic := '0'; ramx_vme_adcx_rd_dma : IN std_logic := '0'; ramx_vme_adcx_rd_cycle : IN std_logic := '0'; ramx_vme_bx_rd_request : IN std_logic := '0'; ramx_vme_rd_fifo_rd_en : IN std_logic := '0'; mca_ram_rd_req : IN std_logic := '0'; mca_ram_rd_addr : IN std_logic_vector(24 downto 0); ram_vme_rd_data_fifo_empty : IN std_logic := '0'; ram_vme_rd_addr_wr_fifo_pipe_empty : IN std_logic := '0'; ram_vme_rd_addr_fifo_pipe_wr_count : IN std_logic_vector(8 downto 0); ram_vme_rd_data_fifo_pipe_rd_count : IN std_logic_vector(8 downto 0); ramx_vme_rd_fifo_empty_out : OUT std_logic := '0'; ramx_vme_rd_gt_out : OUT std_logic := '0'; mca_ram_rd_gt_out : OUT std_logic := '0'; mca_ram_rd_data_valid_out : OUT std_logic := '0'; mca_ram_rd_data_ld1_out : OUT std_logic := '0'; mca_ram_rd_data_ld2_out : OUT std_logic := '0'; ram_vme_rd_data_fifo_rd_en_out : OUT std_logic := '0'; ram_vme_rd_data_fifo_aint_out : OUT std_logic := '0'; ram_vme_rd_addr_fifo_clr_out : OUT std_logic := '0'; ram_vme_rd_addr_fifo_wr_en_out : OUT std_logic := '0'; ram_vme_rd_addr_fifo_d_out : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT vme_ram_test_write_controller PORT( sys_clk_100 : IN std_logic := '0'; ram_write_clk : IN std_logic := '0'; vme_ad_ireg : IN std_logic_vector(31 downto 0); vme_adcx_addr_ld : IN std_logic := '0'; vme_ram_wr_cycle : IN std_logic := '0'; vme_ram_wr_cmd_pulse : IN std_logic := '0'; vme_fpga_test_write_ram_addr_fifo_ce : OUT std_logic := '0'; vme_fpga_test_write_ram_data_fifo_ce : OUT std_logic := '0'; vme_fpga_test_write_ram_addr_fifo_din : OUT std_logic_vector(31 downto 0); vme_fpga_test_write_ram_data_fifo_din : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT vme_intf PORT( MHZ100 : IN std_logic := '0'; fpga_sel : IN std_logic := '0'; fpga_ds : IN std_logic := '0'; fpga_write : IN std_logic := '0'; fpga_block : IN std_logic := '0'; fpga_reset_ibuf : IN std_logic := '0'; fpga_key_reset_ibuf : IN std_logic := '0'; VME_IN_AD : IN std_logic_vector(31 downto 0); adc1_ram_address_counter : IN std_logic_vector(24 downto 0); adc2_ram_address_counter : IN std_logic_vector(24 downto 0); adc1_last_buffer_ram_address_counter : IN std_logic_vector(24 downto 0); adc2_last_buffer_ram_address_counter : IN std_logic_vector(24 downto 0); actual_adc1_data_in : IN std_logic_vector(15 downto 0); actual_adc2_data_in : IN std_logic_vector(15 downto 0); test_in : IN std_logic_vector(31 downto 0); test2_in : IN std_logic_vector(31 downto 0); vme_0x80_feedback_reg : IN std_logic_vector(31 downto 0); vme_0x84_feedback_reg : IN std_logic_vector(31 downto 0); vme_0x88_feedback_reg : IN std_logic_vector(31 downto 0); vme_0x8C_feedback_reg : IN std_logic_vector(31 downto 0); vme_0x90_feedback_reg : IN std_logic_vector(31 downto 0); vme_0x94_feedback_reg : IN std_logic_vector(31 downto 0); vme_0x98_feedback_reg : IN std_logic_vector(31 downto 0); vme_0x9C_feedback_reg : IN std_logic_vector(31 downto 0); bank1_rd_data : IN std_logic_vector(31 downto 0); bank2_rd_data : IN std_logic_vector(31 downto 0); vme_b1_ff_empty : IN std_logic := '0'; vme_b2_ff_empty : IN std_logic := '0'; vme_adc1_event_dir_data : IN std_logic_vector(31 downto 0); vme_adc2_event_dir_data : IN std_logic_vector(31 downto 0); event_config_reg : INOUT std_logic_vector(31 downto 0); vme_end_address_threshold_reg : INOUT std_logic_vector(23 downto 2); vme_pretrigger_delay_reg : INOUT std_logic_vector(15 downto 0); vme_trigger_gate_active_window_reg : INOUT std_logic_vector(15 downto 0); vme_buffer_copy_start_addr_reg : INOUT std_logic_vector(15 downto 0); vme_buffer_copy_length_reg : INOUT std_logic_vector(15 downto 0); trigger_flag_latch_cnt_register : INOUT std_logic_vector(31 downto 0); adc1_trigger_setup : INOUT std_logic_vector(31 downto 0); adc1_trigger_threshold : INOUT std_logic_vector(26 downto 0); adc2_trigger_setup : INOUT std_logic_vector(31 downto 0); adc2_trigger_threshold : INOUT std_logic_vector(26 downto 0); vme_0x40_reg : INOUT std_logic_vector(31 downto 0); vme_0x44_reg : INOUT std_logic_vector(15 downto 0); vme_0x48_reg : INOUT std_logic_vector(15 downto 0); vme_0x4C_reg : INOUT std_logic_vector(15 downto 0); vme_0x50_reg : INOUT std_logic_vector(15 downto 0); vme_0x54_reg : INOUT std_logic_vector(15 downto 0); vme_0x58_reg : INOUT std_logic_vector(15 downto 0); vme_0x5C_reg : INOUT std_logic_vector(15 downto 0); vme_0x60_reg : INOUT std_logic_vector(31 downto 0); vme_0x64_reg : INOUT std_logic_vector(31 downto 0); vme_0x68_reg : INOUT std_logic_vector(7 downto 0); vme_b1_rd : INOUT std_logic := '0'; vme_b2_rd : INOUT std_logic := '0'; vme_adc1_event_dir_rd_ce : INOUT std_logic := '0'; vme_adc2_event_dir_rd_ce : INOUT std_logic := '0'; vme_adcx_event_dir_addr_reg : INOUT std_logic_vector(8 downto 0); wst_out_en : OUT std_logic := '0'; vme_out_wst_oreg : OUT std_logic := '0'; vme_out_ad_en : OUT std_logic := '0'; VME_OUT_AD : OUT std_logic_vector(31 downto 0); vme_b1_addr_ld : OUT std_logic := '0'; vme_b2_addr_ld : OUT std_logic := '0'; vme_b1_rd_cmd : OUT std_logic := '0'; vme_b2_rd_cmd : OUT std_logic := '0'; vme_bx_rd_dma : OUT std_logic := '0'; vme_bx_rd_cycle : OUT std_logic := '0'; vme_bx_rd_request : OUT std_logic := '0'; vme_b1_wr_cycle : OUT std_logic := '0'; vme_b2_wr_cycle : OUT std_logic := '0'; vme_b1_wr_cmd_pulse : OUT std_logic := '0'; vme_b2_wr_cmd_pulse : OUT std_logic ); END COMPONENT; component postransition_to_pulse is port ( clock : in std_logic := '0'; en_clk : in std_logic := '0'; signal_in : in std_logic := '0'; pulse : out std_logic); end component; attribute IOB : string; attribute IOB of InputFD1s: label is "TRUE"; attribute IOB of InputFD2s: label is "TRUE"; attribute IOB of Inst_IFD_SAMPLE_LOGIC_RESET: label is "TRUE"; signal sys_clkfx_out : std_logic := '0'; signal dcm_sys_clock_locked : std_logic := '0'; signal dcm_sys_clock_locked_l : std_logic := '0'; signal ext_trigger_S : std_logic := '0'; signal cmd_start_adc_S : std_logic := '0'; signal cmd_soft_trigger_S : std_logic := '0'; signal cmd_output_select_S : std_logic_vector(3 downto 0) := "0000"; signal cmd_baseline_enable_S : std_logic := '0'; signal cmd_double_CF_S : std_logic := '0'; signal cmd_program_params_S : std_logic := '0'; signal cmd_bypass_mwd_S : std_logic := '0'; signal cmd_bypass_reshape_S : std_logic := '0'; signal cmd_enableFE1_S : std_logic := '0'; signal cmd_enableFE2_S : std_logic := '0'; signal ram1_rd_data_fifo_full : std_logic := '0'; signal ram2_rd_data_fifo_full : std_logic := '0'; signal vme_event_config_ADC1 : std_logic_vector(15 downto 0) := (others => '0'); attribute syn_keep : boolean; -- Using Syn_Keep Derictive attribute syn_keep of clk_int : signal is true; ------------------------------------------------------------------------------------------------------ begin -- fix all undriven pins FPGA_ADC1_TRIGGER_L <= '0'; FPGA_ADC2_TRIGGER_L <= '0'; CON_WITH_ADC78_OUT1_L <= '0'; FPGA_ADC12_EVENT_END_L <= '0'; -- start_up_logic new 25.10.2006 --start_up_logic:process(system_clk_ibufg) -- PL: start_up_logic:process(system_clk_ibufg, new_fpga_reset_ibuf, start_delay10) begin if rising_edge(system_clk_ibufg) then start_delay1 <= '1' ; start_delay2 <= start_delay1 ; start_delay3 <= start_delay2 ; start_delay4 <= start_delay3 ; start_delay5 <= start_delay4 ; start_delay6 <= start_delay5 ; start_delay7 <= start_delay6 ; start_delay8 <= start_delay7 ; start_delay9 <= start_delay8 ; start_delay10 <= start_delay9 ; fpga_reset_ibuf <= (NOT i_fpga_reset_l) or (NOT i_fpga_key_reset_l); -- Peter !! fpga_reset_delay <= fpga_reset_ibuf ; new_fpga_reset_ibuf <= fpga_reset_ibuf and fpga_reset_delay ; end if; rst <= new_fpga_reset_ibuf -- ist nun synchronisiert und deglitched (2 clocks) ; or not start_delay10 ; end process; --****************************************************************** -- system (DDR) clock SYS_CLK_INST : IBUFDS port map (I => system_clk_p, IB => system_clk_n, O => i_system_clk); sys_bufg : BUFG port map ( I => i_system_clk, O => system_clk_ibufg); Inst_sys_clk_dcm: sys_clk_dcm PORT MAP(sys_clk_in => system_clk_ibufg, rst => rst, -- reset ist wichtig; muss active sein , bis system_clk_ibufg sys_clk_out => sys_clk_100, sys_clkfx_out => sys_clkfx_out, dcm_sys_clock_locked => dcm_sys_clock_locked, sys_clk_div2 => open --sys_clk_div2 --peter ); dcm_sys_clock_locked_l <= not dcm_sys_clock_locked ; Inst_ddr_clk_dcm: ddr_clk_dcm PORT MAP( sys_clk => sys_clkfx_out, rst => dcm_sys_clock_locked_l, clk_int => clk_int, clk180_int => clk180_int, clk90_int => clk90_int, clk270_int => clk270_int, dcm_lock => clk_int_dcm_lock, ddr1_clk => ddr1_clk, ddr1_clkb => ddr1_clkb, ddr2_clk => ddr2_clk, ddr2_clkb => ddr2_clkb ); --****************************************************************** -- DDR Ram System Reset --PL: --ram_reset_logic:process(clk180_int) ram_reset_logic:process(clk180_int, rst, clk_int_dcm_lock) begin if ((rst = '1') or (clk_int_dcm_lock = '0') ) then ddr2_clk_system_reset_cnt <= "000000"; ddr2_clk_system_reset <= '1' ; elsif rising_edge(clk180_int) then if (ddr2_clk_system_reset_cnt(5) = '1') then ddr2_clk_system_reset_cnt <= ddr2_clk_system_reset_cnt ; ddr2_clk_system_reset <= '0' ; else ddr2_clk_system_reset_cnt <= ddr2_clk_system_reset_cnt + "000001"; ddr2_clk_system_reset <= '1' ; end if; end if; end process; --****************************************************************** -- adc system clock --****************************************************************** SYS_ADC_CLK_INST : IBUFDS port map (I => system_adc_clk_p, IB => system_adc_clk_n, O => i_system_adc_clk); sys_adc_bufg : BUFG port map ( I => i_system_adc_clk, O => system_adc_clk); OB_OBUFDS1: OBUFDS port map (I => system_adc_clk, O => adc1_clk_out_p, OB => adc1_clk_out_n); OB_OBUFDS2: OBUFDS port map (I => system_adc_clk, O => adc2_clk_out_p, OB => adc2_clk_out_n); --****************************************************************** -- inputs -- MCA Mode Erweiterung -- inputs -- ---------------------- --Inst_IFD_TIMESTAMP_CLR: FD port map (C => system_adc_clk, D => FPGA_ADC_TIMESTAMP_CLR_L, Q => timestamp_clr_l) ; -- Inst_IFD_SAMPLE_LOGIC_RESET: FD port map (C => system_adc_clk, D => FPGA_ADC_SAMPLE_LOGIC_RESET_L, Q => adc_sample_logic_reset_l) ; -- -- tristate (open col.) outputs --PL: was de onderste maar gewoon '0' en '1' op T geeft een tri-state buf voorkomt een drc fout Inst_OBUFT_LED_TIMESTAMP_OVERFLOW : OBUFT port map ( I => '0', T => '1' , O => FPGA_ADC_LED_TIMESTAMP_OVERFLOW_PULSE_L); adc12_event_logic_busy <= '0' ; -- wijziging van PL iob_adc12_busy : FD port map (Q => FPGA_ADC12_BUSY_L, D => not adc12_event_logic_busy, C => system_adc_clk); --****************************************************************** system_adc_clock_sample_logic: process(system_adc_clk) begin if rising_edge (system_adc_clk) then adc_sample_logic_reset <= not adc_sample_logic_reset_l ; end if; end process; --****************************************************************** -- ADC 1 clock --****************************************************************** --********************************** -- Inputs : clock and data UIBUFG1 : IBUFDS port map (I => adc1_dco_p, IB => adc1_dco_n, O => adc1_dco_clk); adc1_bufg : BUFG port map ( I => adc1_dco_clk, O => adc1_clk_l); adc1_clk <= not adc1_clk_l ; InputBuffer: for I in 0 to 15 generate UB11: IBUFDS port map (I => adc1_din_p(I), IB => adc1_din_n(I), O => adc1_buf_din(I)); end generate; InputFD1s: for I in 0 to 15 generate UB12: FD port map (C => adc1_clk, D => adc1_buf_din(I), Q => adc1_din(I)); end generate; --****************************************************************** -- Protocol and triggering --****************************************************************** vme_event_config_ADC1 <= vme_event_config_reg_S(15 downto 0); process(system_adc_clk) begin if rising_edge (system_adc_clk) then if vme_event_config_ADC1(14) = '0' then ext_trigger_S <= FPGA_ADC_PROT14_L; -- trigger_pulse else ext_trigger_S <= (NOT FPGA_ADC_PROT14_L); -- trigger pulse end if; end if; end process; CON_WITH_ADC78_OUT2_L <= '0'; --****************************************************************** -- ADC 1 sampling --****************************************************************** Feature_Extraction1: Feature_Extraction port map(uP_CLK => clk180_int, Reset => adc_sample_logic_reset, ADC_CLK => adc1_clk, ADCin => adc1_din(15 downto 0), invert_data_in => cmd_invert_data_in_S, externaltrigger => ext_trigger_S, softwaretrigger => cmd_soft_trigger_S, cmd_output_select => cmd_output_select_S, --vme_event_config_ADC1(3 downto 0), cmd_start_adc => cmd_start_adc_S, cmd_enableFE => cmd_enableFE1_S, --'1', cmd_baseline_enable => cmd_baseline_enable_S, cmd_double_CF => cmd_double_CF_S, cmd_program_params => cmd_program_params_S, cmd_bypass_mwd => cmd_bypass_mwd_S, cmd_bypass_reshape => cmd_bypass_reshape_S, decay_correction_in => decay_correction_S, reshape_correction_in => reshape_correction_S, buffer_size => buffer_size_S, int_signal_threshold_in => int_signal_threshold_S, mwd_pwr_in => mwd_pwr_S, cf_pwr_in => cf_pwr_S, cf_integral_pwr_in => cf_integral_pwr_S, baseline_pwr_in => baseline_pwr_S, baseline_inhibit_cnt_in => baseline_inhibit_cnt_S, event_inhibit_cnt_in => event_inhibit_cnt_S, fb_flowctrl_running => FE1_running_S, fb_chain_enable => FE1_enable_S, feedback_port0 => feedback_bus0_S, feedback_port1 => feedback_bus1_S, feedback_port2 => feedback_bus4_S(15 downto 0), feedback_port3 => feedback_bus6_S, adc_ram_fifo_data_wr_data => adc1_ram_fifo_data_wr_data, adc_ram_fifo_address => adc1_ram_fifo_addr_wr_addr, adc_ram_fifo_data_wr_ce => adc1_ram_fifo_data_wr_ce, adc_ram_fifo_addr_wr_ce => adc1_ram_fifo_addr_wr_ce, last_buffer_adc_ram_fifo_wr_addr => adc1_last_buffer_adc_ram_fifo_wr_addr ); vme_0x20_reg_S <= (others => '0'); -- to avoid warning feedback_bus4_S(31 downto 16) <= (others => '0'); -- to avoid warning feedback_bus5_S(31 downto 16) <= (others => '0'); -- to avoid warning mca_ram1_rd_req <= '0' ; mca_ram1_rd_addr(24) <= '0' ; mca_ram1_rd_addr(23 downto 0) <= X"000000" ; mca_ram2_rd_req <= '0' ; mca_ram2_rd_addr(24) <= '0' ; mca_ram2_rd_addr(23 downto 0) <= X"000000" ; --****************************************************************** -- ADC 1 Freeze of actual read out values during access --****************************************************************** freeze1_actual_value_logic: process(adc1_clk) begin if rising_edge (adc1_clk) then adc1_clk_fpga_sel_ireg <= fpga_sel_ireg ; end if; end process; --****************************************************************** -- ADC 2 clock --****************************************************************** -- Inputs : clock and data UIBUFG2 : IBUFDS port map (I => adc2_dco_p, IB => adc2_dco_n, O => adc2_dco_clk); adc2_bufg : BUFG port map ( I => adc2_dco_clk, O => adc2_clk_l); adc2_clk <= not adc2_clk_l ; InputBuffer2: for I in 0 to 15 generate UB21: IBUFDS port map (I => adc2_din_p(I), IB => adc2_din_n(I), O => adc2_buf_din(I)); end generate; InputFD2s: for I in 0 to 15 generate UB22: FD port map (C => adc2_clk, D => adc2_buf_din(I), Q => adc2_din(I)); end generate; -- FD_ddr_ba1: FD PORT MAP(C => clk180,D => ddr_ba_out(1),Q => buf_ddr_ba(1)); --****************************************************************** -- ADC 2 sampling --****************************************************************** --vme_event_config_ADC2 <= vme_event_config_reg_S(31 downto 16); Feature_Extraction2: Feature_Extraction port map(uP_CLK => clk180_int, Reset => adc_sample_logic_reset, ADC_CLK => adc2_clk, ADCin => adc2_din(15 downto 0), invert_data_in => cmd_invert_data_in_S, externaltrigger => ext_trigger_S, softwaretrigger => cmd_soft_trigger_S, cmd_output_select => cmd_output_select_S, cmd_start_adc => cmd_start_adc_S, cmd_enableFE => cmd_enableFE2_S, --'1', cmd_baseline_enable => cmd_baseline_enable_S, cmd_double_CF => cmd_double_CF_S, cmd_program_params => cmd_program_params_S, cmd_bypass_mwd => cmd_bypass_mwd_S, cmd_bypass_reshape => cmd_bypass_reshape_S, decay_correction_in => decay_correction_S, reshape_correction_in => reshape_correction_S, buffer_size => buffer_size_S, int_signal_threshold_in => int_signal_threshold_S, mwd_pwr_in => mwd_pwr_S, cf_pwr_in => cf_pwr_S, cf_integral_pwr_in => cf_integral_pwr_S, baseline_pwr_in => baseline_pwr_S, baseline_inhibit_cnt_in => baseline_inhibit_cnt_S, event_inhibit_cnt_in => event_inhibit_cnt_S, fb_flowctrl_running => FE2_running_S, fb_chain_enable => FE2_enable_S, feedback_port0 => feedback_bus2_S, feedback_port1 => feedback_bus3_S, feedback_port2 => feedback_bus5_S(15 downto 0), feedback_port3 => open, adc_ram_fifo_data_wr_data => adc2_ram_fifo_data_wr_data, adc_ram_fifo_address => adc2_ram_fifo_addr_wr_addr, adc_ram_fifo_data_wr_ce => adc2_ram_fifo_data_wr_ce, adc_ram_fifo_addr_wr_ce => adc2_ram_fifo_addr_wr_ce, last_buffer_adc_ram_fifo_wr_addr => adc2_last_buffer_adc_ram_fifo_wr_addr ); --****************************************************************** -- ADC 2 Freeze of actual read out values during access --****************************************************************** freeze2_actual_value_logic: process(adc2_clk) begin if rising_edge (adc2_clk) then adc2_clk_fpga_sel_ireg <= fpga_sel_ireg ; end if; end process; --*** DDR2 Configuration -- ddr_config_register1 <= "001100001000010" ; -- WR=4 CAS Latency 4, Burst Length = 4 ddr_config_register2 <= "0010000000000" ; -- DQS disable ramx_ddr2_delay_sel <= "10111" ; -- B8 --********************************************************************************************* --*** RAM1 DDR2 Controller -- --********************************************************************************************* vme_mca_ram1_read_controller: vme_mca_ram_read_controller PORT MAP(sys_clk_100 => sys_clk_100, reset => ddr2_clk_system_reset, vme_ad_ireg => vme_ad_ireg, vme_adcx_addr_ld => vme_b1_addr_ld, vme_adcx_rd => vme_b1_rd, ramx_vme_adcx_rd_dma => ramx_vme_bx_rd_dma, ramx_vme_adcx_rd_cycle => ramx_vme_bx_rd_cycle, ramx_vme_bx_rd_request => ramx_vme_bx_rd_request, ramx_vme_rd_fifo_rd_en => ram1_vme_rd_fifo_rd_en, ramx_vme_rd_fifo_empty_out => ram1_vme_rd_data_fifo_empty, ramx_vme_rd_gt_out => open, mca_ram_rd_req => mca_ram1_rd_req, mca_ram_rd_addr => mca_ram1_rd_addr(24 downto 0), mca_ram_rd_gt_out => mca_ram1_rd_gt, mca_ram_rd_data_valid_out => mca_ram1_rd_data_valid, mca_ram_rd_data_ld1_out => mca_ram1_rd_data_ld1, mca_ram_rd_data_ld2_out => mca_ram1_rd_data_ld2, ram_vme_rd_data_fifo_empty => ram1_rd_data_fifo_empty, ram_vme_rd_addr_wr_fifo_pipe_empty => ram1_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.8.2009 ram_vme_rd_addr_fifo_pipe_wr_count => ram1_vme_rd_addr_fifo_pipe_wr_count(8 downto 0), ram_vme_rd_data_fifo_pipe_rd_count => ram1_vme_rd_data_fifo_pipe_rd_count(8 downto 0), ram_vme_rd_data_fifo_rd_en_out => ram1_rd_fifo_rd_en, ram_vme_rd_data_fifo_aint_out => ram1_vme_rd_data_fifo_aint, ram_vme_rd_addr_fifo_clr_out => ram1_vme_rd_addr_fifo_clr, ram_vme_rd_addr_fifo_wr_en_out => ram1_vme_rd_addr_fifo_wr_en, ram_vme_rd_addr_fifo_d_out => ram1_vme_rd_addr_fifo_d ); mca_ram1_fifo_rd_logic: process(sys_clk_100) begin if rising_edge (sys_clk_100) then if (mca_ram1_rd_data_ld1 = '1') then mca_ram1_rd_data_fifo_first_word <= ram1_rd_data_fifo_q ; else mca_ram1_rd_data_fifo_first_word <= mca_ram1_rd_data_fifo_first_word ; end if ; end if; if rising_edge (sys_clk_100) then if (mca_ram1_rd_data_ld2 = '1') then mca_ram1_rd_data_fifo_second_word <= ram1_rd_data_fifo_q ; else mca_ram1_rd_data_fifo_second_word <= mca_ram1_rd_data_fifo_second_word ; end if ; end if; end process; ram1_infrastructure: infrastructure PORT MAP(reset_in => ddr2_clk_system_reset, clk_int => clk_int, clk180_int => clk180_int, clk90_int => clk90_int, dcm_lock => clk_int_dcm_lock, rst_calib1 => ram1_ddr2_rst_calib1, ramx_ddr2_delay_sel_val => ramx_ddr2_delay_sel, delay_sel_val1_val => ram1_ddr2_delay_sel, sys_rst_val => ram1_ddr2_sys_rst, sys_rst90_val => ram1_ddr2_sys_rst90, sys_rst180_val => ram1_ddr2_sys_rst180_orig, sys_rst270_val => ram1_ddr2_sys_rst270 ); ram1_ddr2_sys_rst180 <= '1' when (ram1_ddr2_sys_rst180_orig='1') else '0'; ram1_read_vme_address_fifo_pipe_asynch_reset <= ram1_ddr2_sys_rst180 or ram1_vme_rd_addr_fifo_clr ; ram1_read_vme_address_fifo_pipe: ram_address_fifo_pipe PORT MAP(clk_wr => sys_clk_100, clk180 => clk180_int, asynch_reset => ram1_read_vme_address_fifo_pipe_asynch_reset, fifo_input_d => ram1_vme_rd_addr_fifo_d, fifo_input_wr_en => ram1_vme_rd_addr_fifo_wr_en, fifo_pipe_rd_en => ram1_vme_rd_addr_fifo_pipe_rd_en, sy_clk_wr_fifo_pipe_empty => ram1_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.08.2009 bank_row_last_addr_flag => ram1_vme_rd_bank_row_last_addr_flag, bank_row_addr_conflict_flag => ram1_vme_rd_bank_row_addr_conflict_flag, fifo_pipe_burst_valid => ram1_vme_rd_addr_fifo_pipe_burst_valid, fifo_pipe_valid => ram1_vme_rd_addr_fifo_pipe_valid, fifo_pipe_out_reg => ram1_vme_rd_addr_fifo_q, fifo_pipe_wr_count => ram1_vme_rd_addr_fifo_pipe_wr_count ); ram1_vme_rd_data_fifo : blk_asy_fifo_511x32 port map (din => ram1_ddr2_user_output_data, wr_en => ram1_ddr2_user_data_val, wr_clk => clk90_int, -- daten werden mit clk90 uebernommen rd_en => ram1_rd_fifo_rd_en, rd_clk => sys_clk_100, ainit => ram1_vme_rd_data_fifo_aint, dout => ram1_rd_data_fifo_q, full => ram1_rd_data_fifo_full, empty => ram1_rd_data_fifo_empty, wr_count => open, rd_count => ram1_vme_rd_data_fifo_pipe_rd_count ); -- ********************************** -- write to DDR2 ch1_vme_ram_test_write_controller: vme_ram_test_write_controller PORT MAP(sys_clk_100 => sys_clk_100, ram_write_clk => clk180_int, vme_ad_ireg => vme_ad_ireg, vme_adcx_addr_ld => vme_b1_addr_ld, vme_ram_wr_cycle => vme_ram1_wr_cycle, vme_ram_wr_cmd_pulse => vme_ram1_wr_cmd_pulse, vme_fpga_test_write_ram_addr_fifo_ce => ch1_vme_test_write_ram_addr_fifo_ce, vme_fpga_test_write_ram_data_fifo_ce => ch1_vme_test_write_ram_data_fifo_ce, vme_fpga_test_write_ram_addr_fifo_din => ch1_vme_test_write_ram_addr_fifo_din, vme_fpga_test_write_ram_data_fifo_din => ch1_vme_test_write_ram_data_fifo_din ); ram1_ddr2_write_multiplexer: process (clk180_int) begin if rising_edge(clk180_int) then -- mux_adc1_ram_fifo_addr_wr_ce <= adc1_ram_fifo_addr_wr_ce ; -- mux_adc1_ram_fifo_addr_wr_addr <= adc1_ram_fifo_addr_wr_addr ; -- mux_adc1_ram_fifo_data_wr_ce <= adc1_ram_fifo_data_wr_ce ; -- mux_adc1_ram_fifo_data_wr_data <= adc1_ram_fifo_data_wr_data ; -- end if; end process; -- addr ram1_write_address_fifo_pipe: ram_address_fifo_pipe PORT MAP(clk_wr => clk180_int, clk180 => clk180_int, asynch_reset => ram1_ddr2_sys_rst180, fifo_input_d => mux_adc1_ram_fifo_addr_wr_addr, fifo_input_wr_en => mux_adc1_ram_fifo_addr_wr_ce, fifo_pipe_rd_en => ram1_vme_wr_addr_fifo_pipe_rd_en, sy_clk_wr_fifo_pipe_empty => open, -- new 14.08.2009 bank_row_last_addr_flag => ram1_wr_bank_row_last_addr_flag, bank_row_addr_conflict_flag => ram1_wr_bank_row_addr_conflict_flag, fifo_pipe_burst_valid => ram1_wr_addr_fifo_pipe_burst_valid, fifo_pipe_valid => ram1_vme_wr_addr_fifo_pipe_valid, fifo_pipe_out_reg => ram1_vme_wr_addr_fifo_q, fifo_pipe_wr_count => ram1_fifo_pipe_wr_count ); ram1_vme_wr_data_fifoH : blk_asy_fifo_1023x16 port map(din => mux_adc1_ram_fifo_data_wr_data(15 downto 0), wr_en => mux_adc1_ram_fifo_data_wr_ce, wr_clk => clk180_int, rd_en => ram1_vme_wr_fifo_rd_en, rd_clk => clk180_int, ainit => ram1_ddr2_sys_rst180, --ram1_ddr2_sys_rst, mod. 25.10.2006 dout => ram1_ddr2_user_input_data(15 downto 0), -- full => adc1_ram_fifo_data_full, empty => ram1_ddr2_wr_data_rd_empty, wr_count => ram1_ddr2_wr_data_wr_count, rd_count => ram1_ddr2_wr_data_rd_count ); ram1_vme_wr_data_fifoL : blk_asy_fifo_1023x16 port map(din => mux_adc1_ram_fifo_data_wr_data(31 downto 16), wr_en => mux_adc1_ram_fifo_data_wr_ce, wr_clk => clk180_int, rd_en => ram1_vme_wr_fifo_rd_en, rd_clk => clk180_int, ainit => ram1_ddr2_sys_rst180, --ram1_ddr2_sys_rst, mod. 25.10.2006 dout => ram1_ddr2_user_input_data(31 downto 16), -- full => open, empty => open, wr_count => open, rd_count => open ); --temp_24(31) <= ram1_test_error_flag ; temp_24(31 downto 25) <= "0000000" ; temp_24(24 downto 16) <= ram1_fifo_pipe_wr_count(8 downto 0) ; temp_24(15 downto 10) <= "000000" ; temp_24(9 downto 0) <= ram1_ddr2_wr_data_wr_count(9 downto 0) ; temp_28(31 downto 25) <= "0000000" ; temp_28(24 downto 16) <= ram2_fifo_pipe_wr_count(8 downto 0) ; temp_28(15 downto 10) <= "000000" ; temp_28(9 downto 0) <= ram2_ddr2_wr_data_wr_count(9 downto 0) ; ram1_ddr2_readwrite_fsm: ddr2_readwrite_fsm PORT MAP(clk180_int => clk180_int, clk_int_dcm_lock => clk_int_dcm_lock, rst180 => ram1_ddr2_sys_rst180, wr_bank_row_last_addr_flag => ram1_wr_bank_row_last_addr_flag, wr_bank_row_addr_conflict_flag => ram1_wr_bank_row_addr_conflict_flag, wr_addr_fifo_pipe_burst_valid => ram1_wr_addr_fifo_pipe_burst_valid, wr_addr_fifo_pipe_valid => ram1_vme_wr_addr_fifo_pipe_valid, wr_addr_fifo_pipe_rd_en => ram1_vme_wr_addr_fifo_pipe_rd_en, wr_data_fifo_rd_en => ram1_vme_wr_fifo_rd_en, ram_fifo_pipe_wr_count => ram1_fifo_pipe_wr_count, rd_bank_row_last_addr_flag => ram1_vme_rd_bank_row_last_addr_flag, rd_bank_row_addr_conflict_flag => ram1_vme_rd_bank_row_addr_conflict_flag, rd_addr_fifo_pipe_burst_valid => ram1_vme_rd_addr_fifo_pipe_burst_valid, rd_addr_fifo_pipe_valid => ram1_vme_rd_addr_fifo_pipe_valid, rd_addr_fifo_pipe_rd_en => ram1_vme_rd_addr_fifo_pipe_rd_en, rd_addr_mux_en => ram1_rd_addr_mux_en, ddr2_ctrl_command_register => ram1_ddr2_command_register, ddr2_ctrl_burst_done => ram1_ddr2_burst_done, ddr2_ctrl_cmd_ack => ram1_ddr2_cmd_ack, ddr2_ctrl_init => ram1_ddr2_init_done, ddr2_ctrl_ar_done => ram1_ddr2_autorefresh_done ); ram1_ddr2_controller_address(24 downto 0) <= ram1_vme_wr_addr_fifo_q(24 downto 0) when (ram1_rd_addr_mux_en = '0') else ram1_vme_rd_addr_fifo_q(24 downto 0) ; ram1_controller: controller PORT MAP(clk => clk_int, clk180_int => clk180_int, rst0 => ram1_ddr2_sys_rst, rst180 => ram1_ddr2_sys_rst180, address => ram1_ddr2_controller_address(22 downto 0), bank_address => ram1_ddr2_controller_address(24 downto 23), config_register1 => ddr_config_register1, config_register2 => ddr_config_register2, command_register => ram1_ddr2_command_register, burst_done => ram1_ddr2_burst_done, ddr_rasb_cntrl => ram1_ddr2_rasb_cntrl, ddr_casb_cntrl => ram1_ddr2_casb_cntrl, ddr_web_cntrl => ram1_ddr2_web_cntrl, ddr_ba_cntrl => ram1_ddr2_ba_cntrl, ddr_address_cntrl => ram1_ddr2_address_cntrl, ddr_cke_cntrl => ram1_ddr2_cke_cntrl, ddr_csb_cntrl => ram1_ddr2_csb_cntrl, ddr_ODT_cntrl => ram1_ddr2_ODT_cntrl, dqs_enable => ram1_ddr2_dqs_enable, dqs_reset => ram1_ddr2_dqs_reset, write_enable => ram1_ddr2_write_enable, rst_calib => ram1_ddr2_rst_calib1, rst_dqs_div_int => ram1_ddr2_rst_dqs_div_int, cmd_ack => ram1_ddr2_cmd_ack, init => ram1_ddr2_init_done, ar_done => ram1_ddr2_autorefresh_done -- output ); ram1_ddr2_data_path: ddr2_data_path PORT MAP( user_input_data => ram1_ddr2_user_input_data, clk => clk_int, clk180 => clk180_int, clk90 => clk90_int, reset => ram1_ddr2_sys_rst, reset90 => ram1_ddr2_sys_rst90, reset180 => ram1_ddr2_sys_rst180, reset270 => ram1_ddr2_sys_rst270, write_enable => ram1_ddr2_write_enable, rst_dqs_div_in => ram1_ddr2_rst_dqs_div, delay_sel => ram1_ddr2_delay_sel, dqs_int_delay_in0 => ram1_ddr2_dqs_int_delay_in0, dqs_int_delay_in1 => ram1_ddr2_dqs_int_delay_in1, dq_in_rising => ram1_ddr2_dq_in_rising, dq_in_falling => ram1_ddr2_dq_in_falling, u_data_val => ram1_ddr2_user_data_val, user_output_data => ram1_ddr2_user_output_data, write_en_val => ram1_ddr2_write_en_val, write_en_val1 => ram1_ddr2_write_en_val1, reset90_r_val => ram1_ddr2_reset90_r, data_mask_f => ram1_ddr2_data_mask_f, data_mask_r => ram1_ddr2_data_mask_r, write_data_falling => ram1_ddr2_write_data_falling, write_data_rising => ram1_ddr2_write_data_rising, test_fifo_wr_addr => ram1_test_fifo_wr_addr ); ram1_ddr2_iobs: ddr2_iobs PORT MAP( clk0 => clk_int, clk180 => clk180_int, clk90 => clk90_int, ddr_rasb_cntrl => ram1_ddr2_rasb_cntrl, ddr_ODT_cntrl => ram1_ddr2_ODT_cntrl, ddr_casb_cntrl => ram1_ddr2_casb_cntrl, ddr_web_cntrl => ram1_ddr2_web_cntrl, ddr_cke_cntrl => ram1_ddr2_cke_cntrl, ddr_csb_cntrl => ram1_ddr2_csb_cntrl, ddr_address_cntrl => ram1_ddr2_address_cntrl, ddr_ba_cntrl => ram1_ddr2_ba_cntrl, rst_dqs_div_int => ram1_ddr2_rst_dqs_div_int, dqs_reset => ram1_ddr2_dqs_reset, dqs_enable => ram1_ddr2_dqs_enable, ddr_dqs => ddr1_dqs, ddr_dq => ddr1_dq, write_data_falling => ram1_ddr2_write_data_falling, write_data_rising => ram1_ddr2_write_data_rising, write_en_val => ram1_ddr2_write_en_val, write_en_val1 => ram1_ddr2_write_en_val1, reset90_r => ram1_ddr2_reset90_r, data_mask_f => ram1_ddr2_data_mask_f, data_mask_r => ram1_ddr2_data_mask_r, ddr_ODT0 => ddr1_ODT0, ddr_rasb => ddr1_rasb, ddr_casb => ddr1_casb, ddr_web => ddr1_web, ddr_ba => ddr1_ba, ddr_address => ddr1_address, ddr_cke => ddr1_cke, ddr_csb => ddr1_csb, rst_dqs_div => ram1_ddr2_rst_dqs_div, rst_dqs_div_iob => ddr1_rst_dqs_div_iob, dqs_int_delay_in0 => ram1_ddr2_dqs_int_delay_in0, dqs_int_delay_in1 => ram1_ddr2_dqs_int_delay_in1, dq_in_rising => ram1_ddr2_dq_in_rising, dq_in_falling => ram1_ddr2_dq_in_falling, ddr_dm => ddr1_dm ); --PL U0 : OBUFT port map ( I => '0', T => '1' , O => CON_WITH_ADC12_OUT1_L); U1 : OBUFT port map ( I => '0', T => '1' , O => CON_WITH_ADC12_OUT2_L); --PL U20 : OBUFT port map ( I => '0', T => '1' , O => ddr1_dqs_reserve(0)); U21 : OBUFT port map ( I => '0', T => '1' , O => ddr1_dqs_reserve(1)); ddr1_ba2_reserve <= '0' ; -- only to force to use the pad --********************************************************************************************* --*** RAM2 DDR2 Controller -- --********************************************************************************************* vme_mca_ram2_read_controller: vme_mca_ram_read_controller PORT MAP( sys_clk_100 => sys_clk_100, reset => ddr2_clk_system_reset, vme_ad_ireg => vme_ad_ireg, vme_adcx_addr_ld => vme_b2_addr_ld, vme_adcx_rd => vme_b2_rd, ramx_vme_adcx_rd_dma => ramx_vme_bx_rd_dma, ramx_vme_adcx_rd_cycle => ramx_vme_bx_rd_cycle, ramx_vme_bx_rd_request => ramx_vme_bx_rd_request, ramx_vme_rd_fifo_rd_en => ram2_vme_rd_fifo_rd_en, ramx_vme_rd_fifo_empty_out => ram2_vme_rd_data_fifo_empty, ramx_vme_rd_gt_out => open, mca_ram_rd_req => mca_ram2_rd_req, mca_ram_rd_addr => mca_ram2_rd_addr(24 downto 0), mca_ram_rd_gt_out => mca_ram2_rd_gt, mca_ram_rd_data_valid_out => mca_ram2_rd_data_valid, mca_ram_rd_data_ld1_out => mca_ram2_rd_data_ld1, mca_ram_rd_data_ld2_out => mca_ram2_rd_data_ld2, ram_vme_rd_data_fifo_empty => ram2_rd_data_fifo_empty, ram_vme_rd_addr_wr_fifo_pipe_empty => ram2_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.8.2009 ram_vme_rd_addr_fifo_pipe_wr_count => ram2_vme_rd_addr_fifo_pipe_wr_count(8 downto 0), ram_vme_rd_data_fifo_pipe_rd_count => ram2_vme_rd_data_fifo_pipe_rd_count(8 downto 0), ram_vme_rd_data_fifo_rd_en_out => ram2_rd_fifo_rd_en, ram_vme_rd_data_fifo_aint_out => ram2_vme_rd_data_fifo_aint, ram_vme_rd_addr_fifo_clr_out => ram2_vme_rd_addr_fifo_clr, ram_vme_rd_addr_fifo_wr_en_out => ram2_vme_rd_addr_fifo_wr_en, ram_vme_rd_addr_fifo_d_out => ram2_vme_rd_addr_fifo_d ); mca_ram2_fifo_rd_logic: process(sys_clk_100) begin if rising_edge (sys_clk_100) then if (mca_ram2_rd_data_ld1 = '1') then mca_ram2_rd_data_fifo_first_word <= ram2_rd_data_fifo_q ; else mca_ram2_rd_data_fifo_first_word <= mca_ram2_rd_data_fifo_first_word ; end if ; end if; if rising_edge (sys_clk_100) then if (mca_ram2_rd_data_ld2 = '1') then mca_ram2_rd_data_fifo_second_word <= ram2_rd_data_fifo_q ; else mca_ram2_rd_data_fifo_second_word <= mca_ram2_rd_data_fifo_second_word ; end if ; end if; end process; ----ram2_read_vme_address_fifo_pipe_asynch_reset <= ram2_ddr2_sys_rst180 or ram2_vme_rd_addr_fifo_clr ; ram2_read_vme_address_fifo_pipe_asynch_reset <= ram2_ddr2_sys_rst180 ; -- or ram2_vme_rd_addr_fifo_clr ; ram2_read_vme_address_fifo_pipe: ram_address_fifo_pipe PORT MAP(clk_wr => sys_clk_100, clk180 => clk180_int, asynch_reset => ram2_read_vme_address_fifo_pipe_asynch_reset, fifo_input_d => ram2_vme_rd_addr_fifo_d, fifo_input_wr_en => ram2_vme_rd_addr_fifo_wr_en, fifo_pipe_rd_en => ram2_vme_rd_addr_fifo_pipe_rd_en, sy_clk_wr_fifo_pipe_empty => ram2_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.08.2009 bank_row_last_addr_flag => ram2_vme_rd_bank_row_last_addr_flag, bank_row_addr_conflict_flag => ram2_vme_rd_bank_row_addr_conflict_flag, fifo_pipe_burst_valid => ram2_vme_rd_addr_fifo_pipe_burst_valid, fifo_pipe_valid => ram2_vme_rd_addr_fifo_pipe_valid, fifo_pipe_out_reg => ram2_vme_rd_addr_fifo_q, fifo_pipe_wr_count => ram2_vme_rd_addr_fifo_pipe_wr_count ); ram2_vme_rd_data_fifo : blk_asy_fifo_511x32 port map(din => ram2_ddr2_user_output_data, wr_en => ram2_ddr2_user_data_val, wr_clk => clk90_int, -- daten werden mit clk90 uebernommen rd_en => ram2_rd_fifo_rd_en, rd_clk => sys_clk_100, ainit => ram2_vme_rd_data_fifo_aint, dout => ram2_rd_data_fifo_q, full => ram2_rd_data_fifo_full, empty => ram2_rd_data_fifo_empty, wr_count => open, rd_count => ram2_vme_rd_data_fifo_pipe_rd_count ); -- ********************************** -- write to DDR2 ch2_vme_ram_test_write_controller: vme_ram_test_write_controller PORT MAP(sys_clk_100 => sys_clk_100, ram_write_clk => clk180_int, vme_ad_ireg => vme_ad_ireg, vme_adcx_addr_ld => vme_b2_addr_ld, vme_ram_wr_cycle => vme_ram2_wr_cycle, vme_ram_wr_cmd_pulse => vme_ram2_wr_cmd_pulse, vme_fpga_test_write_ram_addr_fifo_ce => ch2_vme_test_write_ram_addr_fifo_ce, vme_fpga_test_write_ram_data_fifo_ce => ch2_vme_test_write_ram_data_fifo_ce, vme_fpga_test_write_ram_addr_fifo_din => ch2_vme_test_write_ram_addr_fifo_din, vme_fpga_test_write_ram_data_fifo_din => ch2_vme_test_write_ram_data_fifo_din ); ram2_ddr2_write_multiplexer: process (clk180_int) begin if rising_edge(clk180_int) then -- mux_adc2_ram_fifo_addr_wr_ce <= adc2_ram_fifo_addr_wr_ce ; -- mux_adc2_ram_fifo_addr_wr_addr <= adc2_ram_fifo_addr_wr_addr ; -- mux_adc2_ram_fifo_data_wr_ce <= adc2_ram_fifo_data_wr_ce ; -- mux_adc2_ram_fifo_data_wr_data <= adc2_ram_fifo_data_wr_data ; -- end if; end process; ram2_write_address_fifo_pipe: ram_address_fifo_pipe PORT MAP(clk_wr => clk180_int, clk180 => clk180_int, asynch_reset => ram2_ddr2_sys_rst180, fifo_input_d => mux_adc2_ram_fifo_addr_wr_addr, fifo_input_wr_en => mux_adc2_ram_fifo_addr_wr_ce, fifo_pipe_rd_en => ram2_vme_wr_addr_fifo_pipe_rd_en, sy_clk_wr_fifo_pipe_empty => open, -- new 14.08.2009 bank_row_last_addr_flag => ram2_wr_bank_row_last_addr_flag, bank_row_addr_conflict_flag => ram2_wr_bank_row_addr_conflict_flag, fifo_pipe_burst_valid => ram2_wr_addr_fifo_pipe_burst_valid, fifo_pipe_valid => ram2_vme_wr_addr_fifo_pipe_valid, fifo_pipe_out_reg => ram2_vme_wr_addr_fifo_q, fifo_pipe_wr_count => ram2_fifo_pipe_wr_count ); ram2_vme_wr_data_fifoH : blk_asy_fifo_1023x16 port map(din => mux_adc2_ram_fifo_data_wr_data(15 downto 0), wr_en => mux_adc2_ram_fifo_data_wr_ce, wr_clk => clk180_int, rd_en => ram2_vme_wr_fifo_rd_en, rd_clk => clk180_int, ainit => ram2_ddr2_sys_rst180, --ram2_ddr2_sys_rst, mod. 25.10.2006 dout => ram2_ddr2_user_input_data(15 downto 0), -- daten werden mit clk90 uebernommen full => adc2_ram_fifo_data_full, empty => open, wr_count => ram2_ddr2_wr_data_wr_count, rd_count => open ); ram2_vme_wr_data_fifoL : blk_asy_fifo_1023x16 port map(din => mux_adc2_ram_fifo_data_wr_data(31 downto 16), wr_en => mux_adc2_ram_fifo_data_wr_ce, wr_clk => clk180_int, rd_en => ram2_vme_wr_fifo_rd_en, rd_clk => clk180_int, ainit => ram2_ddr2_sys_rst180, --ram2_ddr2_sys_rst, mod. 25.10.2006 dout => ram2_ddr2_user_input_data(31 downto 16), -- daten werden mit clk90 uebernommen full => open, empty => open, wr_count => open, rd_count => open ); ram2_ddr2_readwrite_fsm: ddr2_readwrite_fsm PORT MAP(clk180_int => clk180_int, clk_int_dcm_lock => clk_int_dcm_lock, rst180 => ram2_ddr2_sys_rst180, wr_bank_row_last_addr_flag => ram2_wr_bank_row_last_addr_flag, wr_bank_row_addr_conflict_flag => ram2_wr_bank_row_addr_conflict_flag, wr_addr_fifo_pipe_burst_valid => ram2_wr_addr_fifo_pipe_burst_valid, wr_addr_fifo_pipe_valid => ram2_vme_wr_addr_fifo_pipe_valid, wr_addr_fifo_pipe_rd_en => ram2_vme_wr_addr_fifo_pipe_rd_en, wr_data_fifo_rd_en => ram2_vme_wr_fifo_rd_en, ram_fifo_pipe_wr_count => ram2_fifo_pipe_wr_count, rd_bank_row_last_addr_flag => ram2_vme_rd_bank_row_last_addr_flag, rd_bank_row_addr_conflict_flag => ram2_vme_rd_bank_row_addr_conflict_flag, rd_addr_fifo_pipe_burst_valid => ram2_vme_rd_addr_fifo_pipe_burst_valid, rd_addr_fifo_pipe_valid => ram2_vme_rd_addr_fifo_pipe_valid, rd_addr_fifo_pipe_rd_en => ram2_vme_rd_addr_fifo_pipe_rd_en, rd_addr_mux_en => ram2_rd_addr_mux_en, ddr2_ctrl_command_register => ram2_ddr2_command_register, ddr2_ctrl_burst_done => ram2_ddr2_burst_done, ddr2_ctrl_cmd_ack => ram2_ddr2_cmd_ack, ddr2_ctrl_init => ram2_ddr2_init_done, ddr2_ctrl_ar_done => ram2_ddr2_autorefresh_done ); ram2_infrastructure: infrastructure PORT MAP(reset_in => '0', clk_int => clk_int, clk180_int => clk180_int, clk90_int => clk90_int, dcm_lock => clk_int_dcm_lock, rst_calib1 => ram2_ddr2_rst_calib1, ramx_ddr2_delay_sel_val => ramx_ddr2_delay_sel, delay_sel_val1_val => ram2_ddr2_delay_sel, sys_rst_val => ram2_ddr2_sys_rst, sys_rst90_val => ram2_ddr2_sys_rst90, sys_rst180_val => ram2_ddr2_sys_rst180_orig, sys_rst270_val => ram2_ddr2_sys_rst270 ); ram2_ddr2_sys_rst180 <= '1' when (ram2_ddr2_sys_rst180_orig='1') else '0'; ram2_ddr2_controller_address(24 downto 0) <= ram2_vme_wr_addr_fifo_q(24 downto 0) when (ram2_rd_addr_mux_en = '0') else ram2_vme_rd_addr_fifo_q(24 downto 0) ; ram2_controller: controller PORT MAP(clk => clk_int, clk180_int => clk180_int, rst0 => ram2_ddr2_sys_rst, rst180 => ram2_ddr2_sys_rst180, address => ram2_ddr2_controller_address(22 downto 0), bank_address => ram2_ddr2_controller_address(24 downto 23), config_register1 => ddr_config_register1, config_register2 => ddr_config_register2, command_register => ram2_ddr2_command_register, burst_done => ram2_ddr2_burst_done, ddr_rasb_cntrl => ram2_ddr2_rasb_cntrl, ddr_casb_cntrl => ram2_ddr2_casb_cntrl, ddr_web_cntrl => ram2_ddr2_web_cntrl, ddr_ba_cntrl => ram2_ddr2_ba_cntrl, ddr_address_cntrl => ram2_ddr2_address_cntrl, ddr_cke_cntrl => ram2_ddr2_cke_cntrl, ddr_csb_cntrl => ram2_ddr2_csb_cntrl, ddr_ODT_cntrl => ram2_ddr2_ODT_cntrl, dqs_enable => ram2_ddr2_dqs_enable, dqs_reset => ram2_ddr2_dqs_reset, write_enable => ram2_ddr2_write_enable, rst_calib => ram2_ddr2_rst_calib1, rst_dqs_div_int => ram2_ddr2_rst_dqs_div_int, cmd_ack => ram2_ddr2_cmd_ack, init => ram2_ddr2_init_done, ar_done => ram2_ddr2_autorefresh_done -- output ); ram2_ddr2_data_path: ddr2_data_path PORT MAP(user_input_data => ram2_ddr2_user_input_data, clk => clk_int, clk180 => clk180_int, clk90 => clk90_int, reset => ram2_ddr2_sys_rst, reset90 => ram2_ddr2_sys_rst90, reset180 => ram2_ddr2_sys_rst180, reset270 => ram2_ddr2_sys_rst270, write_enable => ram2_ddr2_write_enable, rst_dqs_div_in => ram2_ddr2_rst_dqs_div, delay_sel => ram2_ddr2_delay_sel, dqs_int_delay_in0 => ram2_ddr2_dqs_int_delay_in0, dqs_int_delay_in1 => ram2_ddr2_dqs_int_delay_in1, dq_in_rising => ram2_ddr2_dq_in_rising, dq_in_falling => ram2_ddr2_dq_in_falling, u_data_val => ram2_ddr2_user_data_val, user_output_data => ram2_ddr2_user_output_data, write_en_val => ram2_ddr2_write_en_val, write_en_val1 => ram2_ddr2_write_en_val1, reset90_r_val => ram2_ddr2_reset90_r, data_mask_f => ram2_ddr2_data_mask_f, data_mask_r => ram2_ddr2_data_mask_r, write_data_falling => ram2_ddr2_write_data_falling, write_data_rising => ram2_ddr2_write_data_rising, test_fifo_wr_addr => ram2_test_fifo_wr_addr ); ram2_ddr2_iobs: ddr2_iobs PORT MAP(clk0 => clk_int, clk180 => clk180_int, clk90 => clk90_int, ddr_rasb_cntrl => ram2_ddr2_rasb_cntrl, ddr_ODT_cntrl => ram2_ddr2_ODT_cntrl, ddr_casb_cntrl => ram2_ddr2_casb_cntrl, ddr_web_cntrl => ram2_ddr2_web_cntrl, ddr_cke_cntrl => ram2_ddr2_cke_cntrl, ddr_csb_cntrl => ram2_ddr2_csb_cntrl, ddr_address_cntrl => ram2_ddr2_address_cntrl, ddr_ba_cntrl => ram2_ddr2_ba_cntrl, rst_dqs_div_int => ram2_ddr2_rst_dqs_div_int, dqs_reset => ram2_ddr2_dqs_reset, dqs_enable => ram2_ddr2_dqs_enable, ddr_dqs => ddr2_dqs, ddr_dq => ddr2_dq, write_data_falling => ram2_ddr2_write_data_falling, write_data_rising => ram2_ddr2_write_data_rising, write_en_val => ram2_ddr2_write_en_val, write_en_val1 => ram2_ddr2_write_en_val1, reset90_r => ram2_ddr2_reset90_r, data_mask_f => ram2_ddr2_data_mask_f, data_mask_r => ram2_ddr2_data_mask_r, ddr_ODT0 => ddr2_ODT0, ddr_rasb => ddr2_rasb, ddr_casb => ddr2_casb, ddr_web => ddr2_web, ddr_ba => ddr2_ba, ddr_address => ddr2_address, ddr_cke => ddr2_cke, ddr_csb => ddr2_csb, rst_dqs_div => ram2_ddr2_rst_dqs_div, rst_dqs_div_iob => ddr2_rst_dqs_div_iob, dqs_int_delay_in0 => ram2_ddr2_dqs_int_delay_in0, dqs_int_delay_in1 => ram2_ddr2_dqs_int_delay_in1, dq_in_rising => ram2_ddr2_dq_in_rising, dq_in_falling => ram2_ddr2_dq_in_falling, ddr_dm => ddr2_dm ); U30 : OBUFT port map ( I => '0', T => '1' , O => ddr2_dqs_reserve(0)); U31 : OBUFT port map ( I => '0', T => '1' , O => ddr2_dqs_reserve(1)); ddr2_ba2_reserve <= '0' ; -- only to force to use the pad -- ************************************************************************************************** -- VME Prot IOs -- ************************************************************************************************** vme_adc_prot_IOs : process (sys_clk_100, wst_out_en, vme_out_ad_en) begin -- control in if rising_edge (sys_clk_100) then fpga_sel_ireg <= not i_fpga_sel_l ; fpga_ds_ireg <= not i_fpga_ds_l ; fpga_write_ireg <= not i_fpga_write_l ; fpga_block_ireg <= not i_fpga_block_l ; fpga_key_reset_ibuf <= not i_fpga_key_reset_l ;-- mod. 25.10.2006 end if; -- weil short pulse (Übersprecher) am FPGA ADC78 zu sehen waren if rising_edge (sys_clk_100) then fpga_key_reset_delay1 <= fpga_key_reset_ibuf ;-- mod. 27.3.2009 fpga_key_reset_delay2 <= fpga_key_reset_delay1 ;-- mod. 27.3.2009 fpga_key_reset_degliched <= fpga_key_reset_ibuf and fpga_key_reset_delay1 and fpga_key_reset_delay2;-- mod. 27.3.2009 end if; --control out if (wst_out_en = '0') then wst_out_l_oreg <= 'Z' ; elsif rising_edge(sys_clk_100) then wst_out_l_oreg <= not vme_out_wst ; end if; -- data in if rising_edge (sys_clk_100) then vme_ad_ireg <= io_fpga_ad ; end if; --data out if (vme_out_ad_en = '0') then io_fpga_ad <= (others => 'Z') ; elsif rising_edge(sys_clk_100) then io_fpga_ad <= vme_ad_oreg ; end if; end process; vme_synch_logic : process (sys_clk_100) begin if rising_edge (sys_clk_100) then vme_adc1_ram_address_counter(24 downto 2) <= adc1_ram_fifo_addr_wr_addr(24 downto 2) ; vme_adc1_ram_address_counter(1 downto 0) <= "00" ; vme_adc2_ram_address_counter(24 downto 2) <= adc2_ram_fifo_addr_wr_addr(24 downto 2); vme_adc2_ram_address_counter(1 downto 0) <= "00" ; end if; end process; --------------------------------------------------------------------------------------------------------------- -- single bit command lines --------------------------------------------------------------------------------------------------------------- cmd_start_adc_S <= vme_0x04_reg_S(2); cmd_soft_trigger_S <= vme_0x04_reg_S(3); cmd_output_select_S <= vme_0x04_reg_S(7 downto 4); cmd_invert_data_in_S <= vme_0x04_reg_S(8); cmd_baseline_enable_S <= vme_0x04_reg_S(9); cmd_enableFE1_S <= vme_0x04_reg_S(10); cmd_enableFE2_S <= vme_0x04_reg_S(11); cmd_double_CF_S <= vme_0x04_reg_S(12); cmd_program_params_S <= vme_0x04_reg_S(13); cmd_bypass_mwd_S <= vme_0x04_reg_S(14); cmd_bypass_reshape_S <= vme_0x04_reg_S(15); decay_correction_S <= vme_0x08_reg_S; reshape_correction_S <= vme_0x0C_reg_S; --------------------------------------------------------------------------------------------------------------- -- process-parameter registers --------------------------------------------------------------------------------------------------------------- buffer_size_S <= vme_0x40_reg_S; int_signal_threshold_S <= vme_0x44_reg_S; -- 15-bit reg mwd_pwr_S <= vme_0x48_reg_S(7 downto 0); -- 15-bit reg cf_pwr_S <= vme_0x4c_reg_S(7 downto 0); -- 15-bit reg cf_integral_pwr_S <= vme_0x50_reg_S(7 downto 0); -- 15-bit reg baseline_inhibit_cnt_S <= vme_0x54_reg_S(7 downto 0); -- 15-bit reg event_inhibit_cnt_S <= vme_0x58_reg_S(7 downto 0); -- 15-bit reg baseline_pwr_S <= vme_0x5C_reg_S(7 downto 0); -- 15-bit reg --------------------------------------------------------------------------------------------------------------- vme_0x80_feedback_reg_S(0) <= FE1_running_S; vme_0x80_feedback_reg_S(1) <= FE1_enable_S; vme_0x80_feedback_reg_S(2) <= FE2_running_S; vme_0x80_feedback_reg_S(3) <= FE2_enable_S; vme_0x80_feedback_reg_S(4) <= cmd_invert_data_in_S; vme_0x80_feedback_reg_S(5) <= cmd_double_CF_S; vme_0x80_feedback_reg_S(31 downto 6) <= (others => '0'); --------------------------------------------------------------------------------------------------------------- vme_0x84_feedback_reg_S <= feedback_bus0_S; --------------------------------------------------------------------------------------------------------------- vme_0x88_feedback_reg_S <= feedback_bus1_S; --------------------------------------------------------------------------------------------------------------- vme_0x8C_feedback_reg_S <= feedback_bus2_S; --------------------------------------------------------------------------------------------------------------- vme_0x90_feedback_reg_S <= feedback_bus3_S; --------------------------------------------------------------------------------------------------------------- vme_0x94_feedback_reg_S <= feedback_bus4_S; --------------------------------------------------------------------------------------------------------------- vme_0x98_feedback_reg_S <= feedback_bus5_S; --------------------------------------------------------------------------------------------------------------- vme_0x9C_feedback_reg_S <= feedback_bus6_S; --(others => '0'); Inst_vme_intf: vme_intf PORT MAP(MHZ100 => sys_clk_100, fpga_sel => fpga_sel_ireg, fpga_ds => fpga_ds_ireg, fpga_write => fpga_write_ireg, fpga_block => fpga_block_ireg, fpga_reset_ibuf => new_fpga_reset_ibuf, --fpga_reset_ibuf, mod 25.10.2006 fpga_key_reset_ibuf => fpga_key_reset_degliched, wst_out_en => wst_out_en, vme_out_wst_oreg => vme_out_wst, vme_out_ad_en => vme_out_ad_en, VME_OUT_AD => vme_ad_oreg, VME_IN_AD => vme_ad_ireg, event_config_reg => vme_event_config_reg_S(31 downto 0), vme_end_address_threshold_reg => vme_0x04_reg_S(23 downto 2), vme_pretrigger_delay_reg => vme_0x08_reg_S(31 downto 16), vme_trigger_gate_active_window_reg => vme_0x08_reg_S(15 downto 0), vme_buffer_copy_start_addr_reg => vme_0x0C_reg_S(15 downto 0), vme_buffer_copy_length_reg => vme_0x0C_reg_S(31 downto 16), adc1_ram_address_counter => vme_adc1_ram_address_counter(24 downto 0), adc2_ram_address_counter => vme_adc2_ram_address_counter(24 downto 0), adc1_last_buffer_ram_address_counter => adc1_last_buffer_adc_ram_fifo_wr_addr(24 downto 0), adc2_last_buffer_ram_address_counter => adc2_last_buffer_adc_ram_fifo_wr_addr(24 downto 0), actual_adc1_data_in => vme_0x20_reg_S(31 downto 16), actual_adc2_data_in => vme_0x20_reg_S(15 downto 0), test_in => temp_24, --vme_test_in, test2_in => temp_28, --vme_test2_in, trigger_flag_latch_cnt_register => open, adc1_trigger_setup => vme_0x30_reg_S(31 downto 0), adc1_trigger_threshold => vme_0x34_reg_S(26 downto 0), adc2_trigger_setup => vme_0x38_reg_S(31 downto 0), adc2_trigger_threshold => vme_0x3C_reg_S(26 downto 0), vme_0x40_reg => vme_0x40_reg_S(31 downto 0), vme_0x44_reg => vme_0x44_reg_S(15 downto 0), vme_0x48_reg => vme_0x48_reg_S(15 downto 0), vme_0x4C_reg => vme_0x4C_reg_S(15 downto 0), vme_0x50_reg => vme_0x50_reg_S(15 downto 0), vme_0x54_reg => vme_0x54_reg_S(15 downto 0), vme_0x58_reg => vme_0x58_reg_S(15 downto 0), vme_0x5C_reg => vme_0x5C_reg_S(15 downto 0), vme_0x60_reg => vme_0x60_reg_S(31 downto 0), vme_0x64_reg => vme_0x64_reg_S(31 downto 0), vme_0x68_reg => vme_0x68_reg_S(7 downto 0), vme_0x80_feedback_reg => vme_0x80_feedback_reg_S, vme_0x84_feedback_reg => vme_0x84_feedback_reg_S, vme_0x88_feedback_reg => vme_0x88_feedback_reg_S, vme_0x8C_feedback_reg => vme_0x8C_feedback_reg_S, vme_0x90_feedback_reg => vme_0x90_feedback_reg_S, vme_0x94_feedback_reg => vme_0x94_feedback_reg_S, vme_0x98_feedback_reg => vme_0x98_feedback_reg_S, vme_0x9C_feedback_reg => vme_0x9C_feedback_reg_S, bank1_rd_data => ram1_rd_data_fifo_q, bank2_rd_data => ram2_rd_data_fifo_q, vme_b1_addr_ld => vme_b1_addr_ld, vme_b2_addr_ld => vme_b2_addr_ld, vme_b1_ff_empty => ram1_vme_rd_data_fifo_empty, vme_b2_ff_empty => ram2_vme_rd_data_fifo_empty, vme_b1_rd => vme_b1_rd, vme_b2_rd => vme_b2_rd, vme_b1_rd_cmd => ram1_vme_rd_fifo_rd_en, vme_b2_rd_cmd => ram2_vme_rd_fifo_rd_en, vme_bx_rd_dma => ramx_vme_bx_rd_dma, vme_bx_rd_cycle => ramx_vme_bx_rd_cycle, vme_bx_rd_request => ramx_vme_bx_rd_request, vme_b1_wr_cycle => vme_ram1_wr_cycle, vme_b2_wr_cycle => vme_ram2_wr_cycle, vme_b1_wr_cmd_pulse => vme_ram1_wr_cmd_pulse, vme_b2_wr_cmd_pulse => vme_ram2_wr_cmd_pulse, vme_adc1_event_dir_rd_ce => open, vme_adc2_event_dir_rd_ce => open, vme_adcx_event_dir_addr_reg => open, vme_adc1_event_dir_data => X"00000000", vme_adc2_event_dir_data => X"00000000" ); end Behavioral;