Subversion Repositories reed_solomon_decoder

set_global_assignment -name FAMILY StratixIII
set_global_assignment -name DEVICE EP3SL150F1152C2
set_global_assignment -name TOP_LEVEL_ENTITY RS_dec
set_global_assignment -name VERILOG_FILE "../../rtl/transport_in2out.v"
set_global_assignment -name VERILOG_FILE "../../rtl/RS_dec.v"
set_global_assignment -name VERILOG_FILE "../../rtl/out_stage.v"
set_global_assignment -name VERILOG_FILE "../../rtl/Omega_Phy.v"
set_global_assignment -name VERILOG_FILE "../../rtl/lamda_roots.v"
set_global_assignment -name VERILOG_FILE "../../rtl/input_syndromes.v"
set_global_assignment -name VERILOG_FILE "../../rtl/GF_mult_add_syndromes.v"
set_global_assignment -name VERILOG_FILE "../../rtl/GF_matrix_dec.v"
set_global_assignment -name VERILOG_FILE "../../rtl/GF_matrix_ascending_binary.v"
set_global_assignment -name VERILOG_FILE "../../rtl/error_correction.v"
set_global_assignment -name VERILOG_FILE "../../rtl/DP_RAM.v"
set_global_assignment -name VERILOG_FILE "../../rtl/BM_lamda.v"
set_global_assignment -name USER_LIBRARIES "../../rtl/;"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
set_global_assignment -name DO_COMBINED_ANALYSIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SDC_FILE RS_dec.sdc


set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"