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URL https://opencores.org/ocsvn/riscompatible/riscompatible/trunk

Subversion Repositories riscompatible

[/] [riscompatible/] [trunk/] [sim/] [modelsim/] [compila.do] - Rev 2

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vlib work
vcom -93 ../../rtl/riscompatible_package.vhd
vcom -93 ../../rtl/reg.vhd
vcom -93 ../../rtl/select_and_control.vhd
vcom -93 ../../rtl/ud_package.vhd
vcom -93 ../../rtl/ud.vhd
vcom -93 ../../rtl/ula.vhd
vcom -93 ../../rtl/memory.vhd
vcom -93 ../../rtl/gpio.vhd
vcom -93 ../../rtl/registerbank.vhd
vcom -93 ../../rtl/riscompatible_core.vhd
vcom -93 ../../rtl/riscompatible.vhd
vcom -93 ../../bench/riscompatible_tb.vhd
vsim riscompatible_tb
do wave_riscompatible.do
run 100 us

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