Subversion Repositories soc_auto_vbus

use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
 
package vBUS is
  -- interface declaration
  type TvBUSnodeType is (INPUT, OUTPUT);
  type TvBUSnodeMode is (PART, PREG, WORD, WREG);
  type TvBUSnodeDesc is record
                   name :string(1 to 32);
                    dir :TvBUSnodeType;
                   mode :TvBUSnodeMode;
                   size :positive;
                 end record;
  type TvBUSdesc is array (natural range <>) of TvBUSnodeDesc;
  function vBUSnodeDesc(name :string; dir :TvBUSnodeType; mode :TvBUSnodeMode; size: natural) return TvBUSnodeDesc;
  -- interface configuration
  type TvBUSnodeCfg is record
                      name :string(TvBUSnodeDesc.name'range);
                       dir :TvBUSnodeType;
                      mode :TvBUSnodeMode;
                      size :natural;
                      addr :natural;
                      vpos :natural;
                    end record;
  type TvBUScfg is array (natural range <>) of TvBUSnodeCfg;
  impure function vBUScreator(asize, dsize :positive; desc :TvBUSdesc; fname :string) return TvBUScfg;
  function vBUSlength(cfg :TvBUScfg) return natural;
  -- nodes implementation
  function vBUSnodeWordSize    (name :string; cfg :TvBUScfg) return natural;
  function vBUSnodeOutputData  (name :string; cfg :TvBUScfg; vBUS       :std_logic_vector) return std_logic_vector;
  function vBUSnodeOutputEnable(name :string; cfg :TvBUScfg; vBUS       :std_logic_vector) return std_logic_vector;
  function vBUSnodeInputData   (name :string; cfg :TvBUScfg; vBUS, data :std_logic_vector) return std_logic_vector;
  function vBUSnodeInputEnable (name :string; cfg :TvBUScfg; vBUS       :std_logic_vector) return std_logic_vector;
  -- local interface implementation
  component vBUSinterface is
   generic (
     vBUScfg			:TvBUScfg);
   port(
     resetN			:in    std_logic;
     enableN			:in    std_logic;
     strobeN			:in    std_logic;
     readN			:in    std_logic;
     addr			:in    std_logic_vector;
     data_wr			:in    std_logic_vector;
     data_rd			:out   std_logic_vector;
     vbus			:inout std_logic_vector);
  end component vBUSinterface;
end package;
 
package body vBUS is
 
  function \vBUSname\(name :string) return string is
    variable iname :string(1 to TvBUSnodeDesc.name'length);
  begin
    iname := (others => ' ');
    iname(1 to name'length) := name;
    return(iname);
  end function;
 
  function vBUSnodeDesc(name :string; dir :TvBUSnodeType; mode :TvBUSnodeMode; size: natural) return TvBUSnodeDesc is
    variable item :TvBUSnodeDesc;
  begin
    item.name := \vBUSname\(name);
    item.dir  := dir;
    item.mode := mode;
    item.size := size;
    return(item);
  end function;
 
  impure function vBUScreator(asize, dsize :positive; desc :TvBUSdesc; fname :string) return TvBUScfg is
    variable  vBUS :TvBUScfg(0 to desc'length) := (others => ((others => ' '),INPUT,PART,0,0,0));
    variable  addr, num, vpos :natural := 0;
    file      fid :text open write_mode is fname;
    variable  l : line;
    variable  c : character;
    function \size\(arg :natural) return natural is begin
      for index in 1 to 30 loop
        if (2**index>arg) then return(index); end if;
      end loop;
      return (31);
    end function;
  begin
    -- bus configuration
    for i in 0 to desc'length-1 loop
      num := (desc(i).size-1)/dsize+1;
      vBUS(i+1).name := desc(i).name;
      vBUS(i+1).dir  := desc(i).dir;
      vBUS(i+1).addr := addr;
      vBUS(i+1).size := desc(i).size;
      vBUS(i+1).vpos := vpos;
      vBUS(i+1).mode := desc(i).mode;
      addr := addr + num;
      if (desc(i).dir=OUTPUT) then
        case desc(i).mode is
          when PART => vpos := vpos + num;
          when PREG => vpos := vpos + desc(i).size + num;
          when WORD => vpos := vpos + (num-1)*dsize + 1;
          when WREG => vpos := vpos + desc(i).size + (num-1)*dsize + 1;
        end case;
      else
        case desc(i).mode is
          when PART => vpos := vpos + desc(i).size + num;
          when PREG => vpos := vpos + 2*desc(i).size + num;
          when WORD => vpos := vpos + 2*desc(i).size + 1; if (num>1) then vpos := vpos - dsize; end if;
          when WREG => vpos := vpos + 2*desc(i).size + 1;
        end case;
      end if;
    end loop;
    vBUS(0).addr := asize;
    vBUS(0).size := dsize;
    vBUS(0).vpos := vpos+dsize;
    -- bus configuration checking and description file generation
    assert (addr>0) report "vBUScfg: empty configuration" severity warning;
    assert (\size\(addr-1)<=asize) report "vBUScfg: address size exceeded" severity error;
    write(l,string'("<?xml version=""1.0"" encoding=""ISO-8859-1"" ?>"));  
    writeline(fid,l);
    write(l,string'("<bus name=""vBUS"" addr="""&integer'image(vBUS(0).addr)&""" data="""&integer'image(vBUS(0).size)&""">"));  
    writeline(fid,l);
    vpos := TvBUSnodeCfg.name'length;
    for i in 1 to vBUS'length-1 loop
      for j in i+1 to vBUS'length-1 loop
        assert (vBUS(i).name /= vBUS(0).name) report "vBUScfg: empty name" severity error;
        assert (vBUS(i).name /= vBUS(j).name) report "vBUScfg: names duplicate" severity error;
      end loop;
      num := vpos;
      for j in 1 to vpos loop
        if (vBUS(i).name(j)=' ') then
          num := j-1;
          assert (vBUS(i).name(j to vpos) = vBUS(0).name(j to vpos)) report "vBUScfg: wrong name" severity error;
          exit;
        end if;
      end loop;
      if vBUS(i).dir=INPUT then c:='r'; else c:='w'; end if;
      write(l,string'("  <node name="""&vBUS(i).name(1 to num)&""" permission="""&c&""" addr="""&
                       integer'image(vBUS(i).addr)&""" size="""&integer'image(vBUS(i).size)&"""/>"));
      writeline(fid,l);
    end loop;
    write(l,string'("</bus>"));  
    writeline(fid,l);
    return (vBUS);
  end function;
 
  function vBUSlength(cfg :TvBUScfg) return natural is
  begin
    return(cfg(0).vpos);
  end function;  
 
  function \vBUSnodeIdx\(name :string; cfg :TvBUScfg) return natural is
    variable n :string(1 to TvBUSnodeCfg.name'length);
  begin
    n := (others => ' ');
    n(1 to name'length) := name;
    for i in 1 to cfg'length-1 loop
      if(cfg(i).name=n) then return(i); end if;
    end loop;
    return(0);
  end function;  
 
  function vBUSnodeWordSize(name :string; cfg :TvBUScfg) return natural is
    constant n: natural := \vBUSnodeIdx\(name,cfg);
  begin
    if (n>0) then return(cfg(n).size); end if;
    assert (false) report "vBUSnodeSize: node <" & name & "> not exist" severity error;
    return (0);
  end function;  
 
  function vBUSnodeOutputData(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
    constant n              :natural := \vBUSnodeIdx\(name,cfg);
    variable d              :std_logic_vector(cfg(n).size-1 downto 0);
    variable dv, mv, nv, pv, sv :natural;
  begin
    if (n>0) then
      if (cfg(n).dir=OUTPUT) then
        d  := (others => '0');
        dv := cfg(0).size; mv := dv;
        nv := (cfg(n).size-1)/cfg(0).size+1;
        pv := cfg(n).vpos;
        sv := cfg(n).size;
        for p in 0 to nv-1 loop
          if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
          case cfg(n).mode is
            when PART =>
              d(p*dv+mv-1 downto p*dv) := vBUS(cfg(0).vpos-dv+mv-1 downto cfg(0).vpos-dv);
            when PREG =>
              d(p*dv+mv-1 downto p*dv) := vBUS(pv+p*dv+mv-1 downto pv+p*dv);
            when WORD =>
              if (nv>1 and p<nv-1) then
                d((p+1)*dv-1 downto p*dv) := vBUS(pv+(p+1)*dv-1 downto pv+p*dv);
              else
                d(p*dv+mv-1 downto p*dv) := vBUS(cfg(0).vpos-dv+mv-1 downto cfg(0).vpos-dv);
              end if;
            when WREG =>
              if (nv>1 and p<nv-1) then
                d((p+1)*dv-1 downto p*dv) := vBUS(pv+sv+(p+1)*dv-1 downto pv+sv+p*dv);
              else
                d(p*dv+mv-1 downto p*dv) := vBUS(pv+p*dv+mv-1 downto pv+p*dv);
              end if;
          end case;
        end loop;
        return(d);
      else
        report "vBUSnodeWrData: node <" & name & "> is read only" severity error;
      end if;
    else
      report "vBUSnodeWrData: node <" & name & "> not exist" severity error;
    end if;
    return ("");
  end function;  
 
  function vBUSnodeOutputEnable(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
    constant n              :natural := \vBUSnodeIdx\(name,cfg);
    variable m              :std_logic_vector(cfg(n).size-1 downto 0);
    variable dv, mv, nv, pv, sv :natural;
  begin
    if (n>0) then
      if (cfg(n).dir=OUTPUT) then
        m  := (others => '0');
        dv := cfg(0).size; mv := dv;
        nv := (cfg(n).size-1)/cfg(0).size+1;
        pv := cfg(n).vpos;
        sv := cfg(n).size;
        for p in 0 to nv-1 loop
          if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
          case cfg(n).mode is
            when PART =>
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+p));
            when PREG =>
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+sv+p));
            when WORD =>
              if (p=nv-1) then
                m := (others => vBUS(pv+(nv-1)*dv));
              end if;
            when WREG =>
              if (p=nv-1) then
                m := (others => vBUS(pv+sv+(nv-1)*dv));
              end if;
          end case;
        end loop;
        return(m);
      else
        report "vBUSnodeWrEna: node <" & name & "> is read only" severity error;
      end if;
    else
      report "vBUSnodeWrEna: node <" & name & "> not exist" severity error;
    end if;
    return ("");
  end function;  
 
  function vBUSnodeInputData(name :string; cfg :TvBUScfg; vBUS, data :std_logic_vector) return std_logic_vector is
    constant n: natural := \vBUSnodeIdx\(name,cfg);
    constant d: std_logic_vector(data'length-1 downto 0) := data;
    variable v: std_logic_vector(vBUS'range);
  begin
    if (n>0) then
      if (cfg(n).dir=INPUT) then
        v := (others => 'Z');
        v(cfg(n).vpos+1*cfg(n).size-1 downto 0*cfg(n).size+cfg(n).vpos) := d;
        return(v);
      else
        report "vBUSnodeRdData: node <" & name & "> is write only" severity error;
      end if;
    else
      report "vBUSnodeRdData: node <" & name & "> not exist" severity error;
    end if;
    return ("");
  end function;  
 
  function vBUSnodeInputEnable(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
    constant n              :natural := \vBUSnodeIdx\(name,cfg);
    variable m              :std_logic_vector(cfg(n).size-1 downto 0);
    variable dv, mv, nv, pv, sv :natural;
  begin
    if (n>0) then
      if (cfg(n).dir=INPUT) then
        m  := (others => '0');
        dv := cfg(0).size; mv := dv;
        nv := (cfg(n).size-1)/cfg(0).size+1;
        pv := cfg(n).vpos;
        sv := cfg(n).size;
        for p in 0 to nv-1 loop
          if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
          case cfg(n).mode is
            when PART =>
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+sv+p));
            when PREG =>
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+2*sv+p));
            when WORD =>
              if (nv=1) then
                m := (others => vBUS(pv+sv));
              else
                m := (others => vBUS(pv+2*sv-dv));
              end if;
            when WREG =>
              if (p=nv-1) then
                m := (others => vBUS(pv+2*sv));
              end if;
          end case;
        end loop;
        return(m);
      else
        report "vBUSnodeRdEna: node <" & name & "> is write only" severity error;
      end if;
    else
      report "vBUSnodeRdEna: node <" & name & "> not exist" severity error;
    end if;
    return ("");
  end function;  
 
end package body;
 
---------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.vBUS.all;
 
entity vBUSinterface is
  generic (
    vBUScfg			:TvBUScfg
  );
  port(
    resetN			:in    std_logic;
    enableN			:in    std_logic;
    strobeN			:in    std_logic;
    readN				:in    std_logic;
    addr			:in    std_logic_vector;
    data_wr			:in    std_logic_vector;
    data_rd			:out   std_logic_vector;
    vbus			:inout std_logic_vector
  );
end entity vBUSinterface;
 
architecture behaviour of vBUSinterface is
 
  signal vbus_awr, vbus_swr, vbus_ard, vbus_srd	:std_logic_vector(vbus'range) := (others => '0');
 
begin
 
  async_wr: process (enableN, readN, addr, vbus) is
    variable bv                 :std_logic_vector(vbus'range);
    variable av                 :std_logic;
    variable dv, nv, pv, sv :natural;
  begin
    bv := (others => '0');
    for i in 1 to vBUScfg'length-1 loop
      if (vBUScfg(i).dir=OUTPUT) then
        dv := vBUScfg(0).size;
        nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
        pv := vBUScfg(i).vpos;
        sv := vBUScfg(i).size;
        for p in 0 to nv-1 loop
          if (enableN='0' and readN='1' and vBUScfg(i).addr+p=unsigned(addr)) then av := '1'; else av := '0'; end if;
          case vBUScfg(i).mode is
            when PART =>
              bv(pv+p) := av;
            when PREG =>
              bv(pv+sv+p) := av;
            when WORD =>
              if (p=nv-1) then
                bv(pv+(nv-1)*dv) := av;
              end if;
            when WREG =>
              if (p=nv-1) then
                bv(pv+sv+(nv-1)*dv) := av;
              end if;
          end case;
        end loop;
      end if;
    end loop;
    vbus_awr <= bv;
  end process;
 
  sync_wr: process (resetN, strobeN) is
    variable mv, dv, nv, pv, sv :natural;
  begin
    if (resetN='0') then
      vbus_swr <= (others => '0');
    elsif (strobeN'event and strobeN='1') then
      for i in 1 to vBUScfg'length-1 loop
        if (vBUScfg(i).dir=OUTPUT) then
          dv := vBUScfg(0).size; mv := dv;
          nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
          pv := vBUScfg(i).vpos;
          sv := vBUScfg(i).size;
          for p in 0 to nv-1 loop
            if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
            if (enableN='0' and readN='1' and vBUScfg(i).addr+p=unsigned(addr)) then
              case vBUScfg(i).mode is
                when PART =>
                  null;
                when PREG =>
                  vbus_swr(pv+p*dv+mv-1 downto pv+p*dv) <= data_wr(mv-1 downto 0);
                when WORD =>
                  if (p<nv-1) then
                    vbus_swr(pv+(p+1)*dv-1 downto pv+p*dv) <= data_wr;
                  end if;
                when WREG =>
                  vbus_swr(pv+p*dv+mv-1 downto pv+p*dv) <= data_wr(mv-1 downto 0);
                  if (nv>1 and p=nv-1) then
                    vbus_swr(pv+sv+p*dv-1 downto pv+sv) <= vbus_swr(pv+p*dv-1 downto pv);
                  end if;
              end case;
            end if;
          end loop;
        end if;
      end loop;
    end if;
  end process;
 
  sync_rd: process (resetN, strobeN) is
    variable mv, dv, nv, pv, sv :natural;
  begin
    if (resetN='0') then
      vbus_srd <= (others => '0');
    elsif (strobeN'event and strobeN='0') then
      for i in 1 to vBUScfg'length-1 loop
        if (vBUScfg(i).dir=INPUT) then
          dv := vBUScfg(0).size; mv := dv;
          nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
          pv := vBUScfg(i).vpos;
          sv := vBUScfg(i).size;
          for p in 0 to nv-1 loop
            if(enableN='0' and readN='0' and vBUScfg(i).addr+p=unsigned(addr)) then
              if (p=nv-1) then mv := sv-(nv-1)*vBUScfg(0).size; end if;
              case vBUScfg(i).mode is
                when PART =>
                  null;
                when PREG =>
                  vbus_srd(pv+sv+p*dv+mv-1 downto pv+sv+p*dv) <= vbus(pv+p*dv+mv-1 downto pv+p*dv);
                when WORD =>
                  if (p=0 and nv>1) then
                    vbus_srd(pv+2*sv-dv-1 downto pv+sv) <= vbus(pv+sv-1 downto pv+dv);
                  end if;
                when WREG =>
                  if (p=0) then
                    vbus_srd(pv+2*sv-1 downto pv+1*sv) <= vbus(pv+1*sv-1 downto pv);
                  end if;
              end case;
            end if;
          end loop;
        end if;
      end loop;
    end if;
  end process;
 
  async_rd: process (enableN, readN, addr, vbus) is
    variable bv                 :std_logic_vector(vbus'range);
    variable dr, dp, dm         :std_logic_vector(vBUScfg(0).size-1 downto 0);
    variable mv, dv, nv, pv, sv :natural;
  begin
    bv := (others => '0');
    dr := (others => '0');
    for i in 1 to vBUScfg'length-1 loop
      if (vBUScfg(i).dir=INPUT) then
        dv := vBUScfg(0).size; mv := dv;
        nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
        pv := vBUScfg(i).vpos;
        sv := vBUScfg(i).size;
        dp := (others => '0');
        for p in 0 to nv-1 loop
          if (p=nv-1) then mv := sv-(nv-1)*vBUScfg(0).size; end if;
          dm := (others => '0');
          if (enableN='0' and readN='0' and vBUScfg(i).addr+p=unsigned(addr)) then dm := (others => '1'); end if;
          case vBUScfg(i).mode is
            when PART =>
              bv(pv+sv+p) := dm(0);
              dp(mv-1 downto 0) := vbus(pv+p*dv+mv-1 downto pv+p*dv);
            when PREG =>
              bv(pv+2*sv+p) := dm(0);
              dp(mv-1 downto 0) := vbus(pv+sv+p*dv+mv-1 downto pv+sv+p*dv);
            when WORD =>
              if (p=0) then
                if (nv=1) then
                  bv(pv+sv) := dm(0);
                else
                  bv(pv+2*sv-dv) := dm(0);
                end if;
                dp(mv-1 downto 0) := vbus(pv+mv-1 downto pv);
              else
                dp(mv-1 downto 0) := vbus(pv+sv+(p-1)*dv+mv-1 downto pv+sv+(p-1)*dv);
              end if;
            when WREG =>
              if (p=0) then
                bv(pv+2*sv) := dm(0);
              end if;
              dp(mv-1 downto 0) := vbus(pv+sv+p*dv+mv-1 downto pv+sv+p*dv);
          end case;
          dr(mv-1 downto 0) := dr(mv-1 downto 0) or (dp(mv-1 downto 0) and dm(mv-1 downto 0));
        end loop;
      end if;
    end loop;
    vbus_ard <= bv;
    data_rd  <= dr;
  end process;
 
  async_vec: process (vbus_awr, vbus_swr, vbus_srd, vbus_ard, data_wr, enableN, strobeN, resetN) is
    variable bv :std_logic_vector(vbus'range);
  begin
    bv := vbus_awr or vbus_ard or vbus_swr or vbus_srd;
    for i in 1 to vBUScfg'length-1 loop
      if (vBUScfg(i).dir=INPUT) then
        bv(vBUScfg(i).size+vBUScfg(i).vpos-1 downto vBUScfg(i).vpos) := (others => 'Z');
      end if;
    end loop;
    bv(bv'length-1 downto bv'length-vBUScfg(0).size) := data_wr;
    vbus <= bv;
  end process;
 
end behaviour;
 
---------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.vBUS.all;
 
entity vBUS_TEST_A_SUM is
  generic (vBUScfg :TvBUScfg);
  port    (vBUS    :inout std_logic_vector);
end entity vBUS_TEST_A_SUM;
 
architecture behaviour of vBUS_TEST_A_SUM is
  signal arg1D :std_logic_vector(vBUSnodeWordSize("arg1", vBUScfg)-1 downto 0);
  signal arg2D :std_logic_vector(vBUSnodeWordSize("arg2", vBUScfg)-1 downto 0);
  signal sumD  :std_logic_vector(vBUSnodeWordSize("sum",  vBUScfg)-1 downto 0);
begin
  sumD  <= unsigned(arg1D) + unsigned(arg2D);
  arg1D <= vBUSnodeOutputData("arg1", vBUScfg, vBUS);
  arg2D <= vBUSnodeOutputData("arg2", vBUScfg, vBUS);
  vBUS  <= vBUSnodeInputData ("sum",  vBUScfg, vBUS, sumD);
end behaviour;
 
---------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.vBUS.all;
 
entity vBUS_TEST_A_MULT is
  generic (vBUScfg :TvBUScfg);
  port    (vBUS    :inout std_logic_vector);
end entity vBUS_TEST_A_MULT;
 
architecture behaviour of vBUS_TEST_A_MULT is
  signal arg1D :std_logic_vector(vBUSnodeWordSize("arg1", vBUScfg)-1 downto 0);
  signal arg2D :std_logic_vector(vBUSnodeWordSize("arg2", vBUScfg)-1 downto 0);
  signal multD :std_logic_vector(vBUSnodeWordSize("mult", vBUScfg)-1 downto 0);
begin
  multD <= unsigned(arg1D) * unsigned(arg2D);
  arg1D <= vBUSnodeOutputData("arg1", vBUScfg, vBUS);
  arg2D <= vBUSnodeOutputData("arg2", vBUScfg, vBUS);
  vBUS  <= vBUSnodeInputData ("mult", vBUScfg, vBUS, multD);
end behaviour;
 
---------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.vBUS.all;
 
entity vBUS_TEST_B is
  generic (
    ADDR_WIDTH			:natural := 4;
    DATA_WIDTH			:natural := 4
  );
  port(
    resetN			:in  std_logic;
    enableN			:in  std_logic;
    strobeN			:in  std_logic;
    readN			:in  std_logic;
    addr			:in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_wr			:in  std_logic_vector(DATA_WIDTH-1 downto 0);
    data_rd			:out std_logic_vector(DATA_WIDTH-1 downto 0)
  );
end entity vBUS_TEST_B;
 
architecture behaviour of vBUS_TEST_B is
 
  constant vBUSdesc :TvBUSdesc := (vBUSnodeDesc("arg1", OUTPUT, WREG, 2*ADDR_WIDTH),
                                   vBUSnodeDesc("arg2", OUTPUT, WREG, 2*ADDR_WIDTH),
                                   vBUSnodeDesc("mult", INPUT,  PART, 4*ADDR_WIDTH),
                                   vBUSnodeDesc("sum",  INPUT,  PART, 2*ADDR_WIDTH));
  constant vBUScfg   :TvBUScfg := vBUScreator(ADDR_WIDTH, DATA_WIDTH, vBUSdesc, "C:\Home\Pozniak\Projekty\vhdl\tests\src\var\bus_config.xml");
  signal   vBUS      :std_logic_vector(vBUSlength(vBUScfg)-1 downto 0);
 
begin
  interf: vBUSinterface generic map (vBUScfg) port map (resetN, enableN, strobeN, readN, addr, data_wr, data_rd, vBUS);
 
  sum:  entity work.vBUS_TEST_A_SUM  generic map (vBUScfg) port map (vBUS);
  mult: entity work.vBUS_TEST_A_MULT generic map (vBUScfg) port map (vBUS);
end behaviour;
 
---------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.vBUS.all;
 
entity vBUS_TEST_A is
  generic (
    ADDR_WIDTH			:natural := 3;
    DATA_WIDTH			:natural := 4;
    ITEM_MODE			:TvBUSnodeMode := PART
  );
  port(
    resetN			:in  std_logic;
    enableN			:in  std_logic;
    strobeN			:in  std_logic;
    readN			:in  std_logic;
    addr			:in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    data_wr			:in  std_logic_vector(DATA_WIDTH-1 downto 0);
    data_rd			:out std_logic_vector(DATA_WIDTH-1 downto 0);
    sdata_output                :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
    sena_output                 :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
    ldata_output                :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
    lena_output                 :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
    sdata_input                 :in  std_logic_vector(DATA_WIDTH/2-1 downto 0);
    sena_input                  :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
    ldata_input                 :in  std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
    lena_input                  :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0)
  );
end entity vBUS_TEST_A;
 
architecture behaviour of vBUS_TEST_A is
  constant vBUSdesc :TvBUSdesc := (vBUSnodeDesc("soutput", OUTPUT, ITEM_MODE, sdata_output'length),
                                   vBUSnodeDesc("loutput", OUTPUT, ITEM_MODE, ldata_output'length),
                                   vBUSnodeDesc("sinput",  INPUT,  ITEM_MODE, sdata_input'length),
                                   vBUSnodeDesc("linput",  INPUT,  ITEM_MODE, ldata_input'length));
  constant vBUScfg   :TvBUScfg := vBUScreator(ADDR_WIDTH, DATA_WIDTH, vBUSdesc, "C:\Home\Pozniak\Projekty\vhdl\tests\src\var\bus_config.xml");
  signal   vBUS      :std_logic_vector(vBUSlength(vBUScfg)-1 downto 0);
begin
  i: vBUSinterface generic map (vBUScfg) port map (resetN, enableN, strobeN, readN, addr, data_wr, data_rd, vBUS);
 
  sdata_output <= vBUSnodeOutputData  ("soutput", vBUScfg, vBUS);
  sena_output  <= vBUSnodeOutputEnable("soutput", vBUScfg, vBUS);
  ldata_output <= vBUSnodeOutputData  ("loutput", vBUScfg, vBUS);
  lena_output  <= vBUSnodeOutputEnable("loutput", vBUScfg, vBUS);
  vBUS         <= vBUSnodeInputData   ("sinput",  vBUScfg, vBUS, sdata_input);
  sena_input   <= vBUSnodeInputEnable ("sinput",  vBUScfg, vBUS);
  vBUS         <= vBUSnodeInputData   ("linput",  vBUScfg, vBUS, ldata_input);
  lena_input   <= vBUSnodeInputEnable ("linput",  vBUScfg, vBUS);
end behaviour;