Subversion Repositories socgen

v 20100214 1
B 300 0  3800 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2650   5 10 1 1 0 0 1 1
device=adv_dbg_if_cpu0
T 400 2850 5 10 1 1 0 0 1 1
refdes=U?
T 400 3000    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 3000    0 10 0 1 0 0 1 1
library=adv_debug_sys
T 400 3000    0 10 0 1 0 0 1 1
component=adv_dbg_if
T 400 3000    0 10 0 1 0 0 1 1
version=cpu0
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=cpu0_data_i[31:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1  
{
T 400 400 5 10 1 1 0 1 1 1 
pinnumber=update_dr_i
T 400 400 5 10 0 1 0 1 1 1 
pinseq=2
}
P 300 600 0 600 4 0 1  
{
T 400 600 5 10 1 1 0 1 1 1 
pinnumber=tdi_i
T 400 600 5 10 0 1 0 1 1 1 
pinseq=3
}
P 300 800 0 800 4 0 1  
{
T 400 800 5 10 1 1 0 1 1 1 
pinnumber=tck_i
T 400 800 5 10 0 1 0 1 1 1 
pinseq=4
}
P 300 1000 0 1000 4 0 1  
{
T 400 1000 5 10 1 1 0 1 1 1 
pinnumber=shift_dr_i
T 400 1000 5 10 0 1 0 1 1 1 
pinseq=5
}
P 300 1200 0 1200 4 0 1  
{
T 400 1200 5 10 1 1 0 1 1 1 
pinnumber=rst_i
T 400 1200 5 10 0 1 0 1 1 1 
pinseq=6
}
P 300 1400 0 1400 4 0 1  
{
T 400 1400 5 10 1 1 0 1 1 1 
pinnumber=debug_select_i
T 400 1400 5 10 0 1 0 1 1 1 
pinseq=7
}
P 300 1600 0 1600 4 0 1  
{
T 400 1600 5 10 1 1 0 1 1 1 
pinnumber=cpu0_clk_i
T 400 1600 5 10 0 1 0 1 1 1 
pinseq=8
}
P 300 1800 0 1800 4 0 1  
{
T 400 1800 5 10 1 1 0 1 1 1 
pinnumber=cpu0_bp_i
T 400 1800 5 10 0 1 0 1 1 1 
pinseq=9
}
P 300 2000 0 2000 4 0 1  
{
T 400 2000 5 10 1 1 0 1 1 1 
pinnumber=cpu0_ack_i
T 400 2000 5 10 0 1 0 1 1 1 
pinseq=10
}
P 300 2200 0 2200 4 0 1  
{
T 400 2200 5 10 1 1 0 1 1 1 
pinnumber=capture_dr_i
T 400 2200 5 10 0 1 0 1 1 1 
pinseq=11
}
P 4100 200 4400 200 10 1 1
{
T 4000 200 5  10 1 1 0 7 1 1 
pinnumber=cpu0_data_o[31:0]
T 4000 200 5  10 0 1 0 7 1 1 
pinseq=12
}
P 4100 400 4400 400 10 1 1
{
T 4000 400 5  10 1 1 0 7 1 1 
pinnumber=cpu0_addr_o[31:0]
T 4000 400 5  10 0 1 0 7 1 1 
pinseq=13
}
P 4100 600 4400 600 4 0 1
{
T 4000 600 5  10 1 1 0 7 1 1
pinnumber=tdo_o
T 4100 600 5  10 0 1 0 7 1 1
pinseq=14
}
P 4100 800 4400 800 4 0 1
{
T 4000 800 5  10 1 1 0 7 1 1
pinnumber=cpu0_we_o
T 4100 800 5  10 0 1 0 7 1 1
pinseq=15
}
P 4100 1000 4400 1000 4 0 1
{
T 4000 1000 5  10 1 1 0 7 1 1
pinnumber=cpu0_stb_o
T 4100 1000 5  10 0 1 0 7 1 1
pinseq=16
}
P 4100 1200 4400 1200 4 0 1
{
T 4000 1200 5  10 1 1 0 7 1 1
pinnumber=cpu0_stall_o
T 4100 1200 5  10 0 1 0 7 1 1
pinseq=17
}
P 4100 1400 4400 1400 4 0 1
{
T 4000 1400 5  10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 4100 1400 5  10 0 1 0 7 1 1
pinseq=18
}