Subversion Repositories socgen

v 20100214 1
B 300 0  4000 6100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 6250   5 10 1 1 0 0 1 1
device=adv_dbg_if_wb_cpu2_jsp
T 400 6450 5 10 1 1 0 0 1 1
refdes=U?
T 400 6600    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 6600    0 10 0 1 0 0 1 1
library=adv_debug_sys
T 400 6600    0 10 0 1 0 0 1 1
component=adv_dbg_if
T 400 6600    0 10 0 1 0 0 1 1
version=wb_cpu2_jsp
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_sel_i[3:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_dat_i[31:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1 
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_cti_i[2:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1 
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_bte_i[1:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1 
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=wb_jsp_adr_i[31:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 10 1 1 
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=wb_dat_i[31:0]
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 10 1 1 
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=cpu1_data_i[31:0]
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 10 1 1 
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=cpu0_data_i[31:0]
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1  
{
T 400 1800 5 10 1 1 0 1 1 1 
pinnumber=wb_rst_i
T 400 1800 5 10 0 1 0 1 1 1 
pinseq=9
}
P 300 2000 0 2000 4 0 1  
{
T 400 2000 5 10 1 1 0 1 1 1 
pinnumber=wb_jsp_we_i
T 400 2000 5 10 0 1 0 1 1 1 
pinseq=10
}
P 300 2200 0 2200 4 0 1  
{
T 400 2200 5 10 1 1 0 1 1 1 
pinnumber=wb_jsp_stb_i
T 400 2200 5 10 0 1 0 1 1 1 
pinseq=11
}
P 300 2400 0 2400 4 0 1  
{
T 400 2400 5 10 1 1 0 1 1 1 
pinnumber=wb_jsp_cyc_i
T 400 2400 5 10 0 1 0 1 1 1 
pinseq=12
}
P 300 2600 0 2600 4 0 1  
{
T 400 2600 5 10 1 1 0 1 1 1 
pinnumber=wb_jsp_cab_i
T 400 2600 5 10 0 1 0 1 1 1 
pinseq=13
}
P 300 2800 0 2800 4 0 1  
{
T 400 2800 5 10 1 1 0 1 1 1 
pinnumber=wb_err_i
T 400 2800 5 10 0 1 0 1 1 1 
pinseq=14
}
P 300 3000 0 3000 4 0 1  
{
T 400 3000 5 10 1 1 0 1 1 1 
pinnumber=wb_clk_i
T 400 3000 5 10 0 1 0 1 1 1 
pinseq=15
}
P 300 3200 0 3200 4 0 1  
{
T 400 3200 5 10 1 1 0 1 1 1 
pinnumber=wb_ack_i
T 400 3200 5 10 0 1 0 1 1 1 
pinseq=16
}
P 300 3400 0 3400 4 0 1  
{
T 400 3400 5 10 1 1 0 1 1 1 
pinnumber=update_dr_i
T 400 3400 5 10 0 1 0 1 1 1 
pinseq=17
}
P 300 3600 0 3600 4 0 1  
{
T 400 3600 5 10 1 1 0 1 1 1 
pinnumber=tdi_i
T 400 3600 5 10 0 1 0 1 1 1 
pinseq=18
}
P 300 3800 0 3800 4 0 1  
{
T 400 3800 5 10 1 1 0 1 1 1 
pinnumber=tck_i
T 400 3800 5 10 0 1 0 1 1 1 
pinseq=19
}
P 300 4000 0 4000 4 0 1  
{
T 400 4000 5 10 1 1 0 1 1 1 
pinnumber=shift_dr_i
T 400 4000 5 10 0 1 0 1 1 1 
pinseq=20
}
P 300 4200 0 4200 4 0 1  
{
T 400 4200 5 10 1 1 0 1 1 1 
pinnumber=rst_i
T 400 4200 5 10 0 1 0 1 1 1 
pinseq=21
}
P 300 4400 0 4400 4 0 1  
{
T 400 4400 5 10 1 1 0 1 1 1 
pinnumber=debug_select_i
T 400 4400 5 10 0 1 0 1 1 1 
pinseq=22
}
P 300 4600 0 4600 4 0 1  
{
T 400 4600 5 10 1 1 0 1 1 1 
pinnumber=cpu1_clk_i
T 400 4600 5 10 0 1 0 1 1 1 
pinseq=23
}
P 300 4800 0 4800 4 0 1  
{
T 400 4800 5 10 1 1 0 1 1 1 
pinnumber=cpu1_bp_i
T 400 4800 5 10 0 1 0 1 1 1 
pinseq=24
}
P 300 5000 0 5000 4 0 1  
{
T 400 5000 5 10 1 1 0 1 1 1 
pinnumber=cpu1_ack_i
T 400 5000 5 10 0 1 0 1 1 1 
pinseq=25
}
P 300 5200 0 5200 4 0 1  
{
T 400 5200 5 10 1 1 0 1 1 1 
pinnumber=cpu0_clk_i
T 400 5200 5 10 0 1 0 1 1 1 
pinseq=26
}
P 300 5400 0 5400 4 0 1  
{
T 400 5400 5 10 1 1 0 1 1 1 
pinnumber=cpu0_bp_i
T 400 5400 5 10 0 1 0 1 1 1 
pinseq=27
}
P 300 5600 0 5600 4 0 1  
{
T 400 5600 5 10 1 1 0 1 1 1 
pinnumber=cpu0_ack_i
T 400 5600 5 10 0 1 0 1 1 1 
pinseq=28
}
P 300 5800 0 5800 4 0 1  
{
T 400 5800 5 10 1 1 0 1 1 1 
pinnumber=capture_dr_i
T 400 5800 5 10 0 1 0 1 1 1 
pinseq=29
}
P 4300 200 4600 200 10 1 1
{
T 4200 200 5  10 1 1 0 7 1 1 
pinnumber=wb_sel_o[3:0]
T 4200 200 5  10 0 1 0 7 1 1 
pinseq=30
}
P 4300 400 4600 400 10 1 1
{
T 4200 400 5  10 1 1 0 7 1 1 
pinnumber=wb_jsp_dat_o[31:0]
T 4200 400 5  10 0 1 0 7 1 1 
pinseq=31
}
P 4300 600 4600 600 10 1 1
{
T 4200 600 5  10 1 1 0 7 1 1 
pinnumber=wb_dat_o[31:0]
T 4200 600 5  10 0 1 0 7 1 1 
pinseq=32
}
P 4300 800 4600 800 10 1 1
{
T 4200 800 5  10 1 1 0 7 1 1 
pinnumber=wb_cti_o[2:0]
T 4200 800 5  10 0 1 0 7 1 1 
pinseq=33
}
P 4300 1000 4600 1000 10 1 1
{
T 4200 1000 5  10 1 1 0 7 1 1 
pinnumber=wb_bte_o[1:0]
T 4200 1000 5  10 0 1 0 7 1 1 
pinseq=34
}
P 4300 1200 4600 1200 10 1 1
{
T 4200 1200 5  10 1 1 0 7 1 1 
pinnumber=wb_adr_o[31:0]
T 4200 1200 5  10 0 1 0 7 1 1 
pinseq=35
}
P 4300 1400 4600 1400 10 1 1
{
T 4200 1400 5  10 1 1 0 7 1 1 
pinnumber=cpu1_data_o[31:0]
T 4200 1400 5  10 0 1 0 7 1 1 
pinseq=36
}
P 4300 1600 4600 1600 10 1 1
{
T 4200 1600 5  10 1 1 0 7 1 1 
pinnumber=cpu1_addr_o[31:0]
T 4200 1600 5  10 0 1 0 7 1 1 
pinseq=37
}
P 4300 1800 4600 1800 10 1 1
{
T 4200 1800 5  10 1 1 0 7 1 1 
pinnumber=cpu0_data_o[31:0]
T 4200 1800 5  10 0 1 0 7 1 1 
pinseq=38
}
P 4300 2000 4600 2000 10 1 1
{
T 4200 2000 5  10 1 1 0 7 1 1 
pinnumber=cpu0_addr_o[31:0]
T 4200 2000 5  10 0 1 0 7 1 1 
pinseq=39
}
P 4300 2200 4600 2200 4 0 1
{
T 4200 2200 5  10 1 1 0 7 1 1
pinnumber=wb_we_o
T 4300 2200 5  10 0 1 0 7 1 1
pinseq=40
}
P 4300 2400 4600 2400 4 0 1
{
T 4200 2400 5  10 1 1 0 7 1 1
pinnumber=wb_stb_o
T 4300 2400 5  10 0 1 0 7 1 1
pinseq=41
}
P 4300 2600 4600 2600 4 0 1
{
T 4200 2600 5  10 1 1 0 7 1 1
pinnumber=wb_jsp_err_o
T 4300 2600 5  10 0 1 0 7 1 1
pinseq=42
}
P 4300 2800 4600 2800 4 0 1
{
T 4200 2800 5  10 1 1 0 7 1 1
pinnumber=wb_jsp_ack_o
T 4300 2800 5  10 0 1 0 7 1 1
pinseq=43
}
P 4300 3000 4600 3000 4 0 1
{
T 4200 3000 5  10 1 1 0 7 1 1
pinnumber=wb_cyc_o
T 4300 3000 5  10 0 1 0 7 1 1
pinseq=44
}
P 4300 3200 4600 3200 4 0 1
{
T 4200 3200 5  10 1 1 0 7 1 1
pinnumber=wb_cab_o
T 4300 3200 5  10 0 1 0 7 1 1
pinseq=45
}
P 4300 3400 4600 3400 4 0 1
{
T 4200 3400 5  10 1 1 0 7 1 1
pinnumber=tdo_o
T 4300 3400 5  10 0 1 0 7 1 1
pinseq=46
}
P 4300 3600 4600 3600 4 0 1
{
T 4200 3600 5  10 1 1 0 7 1 1
pinnumber=int_o
T 4300 3600 5  10 0 1 0 7 1 1
pinseq=47
}
P 4300 3800 4600 3800 4 0 1
{
T 4200 3800 5  10 1 1 0 7 1 1
pinnumber=cpu1_we_o
T 4300 3800 5  10 0 1 0 7 1 1
pinseq=48
}
P 4300 4000 4600 4000 4 0 1
{
T 4200 4000 5  10 1 1 0 7 1 1
pinnumber=cpu1_stb_o
T 4300 4000 5  10 0 1 0 7 1 1
pinseq=49
}
P 4300 4200 4600 4200 4 0 1
{
T 4200 4200 5  10 1 1 0 7 1 1
pinnumber=cpu1_stall_o
T 4300 4200 5  10 0 1 0 7 1 1
pinseq=50
}
P 4300 4400 4600 4400 4 0 1
{
T 4200 4400 5  10 1 1 0 7 1 1
pinnumber=cpu1_rst_o
T 4300 4400 5  10 0 1 0 7 1 1
pinseq=51
}
P 4300 4600 4600 4600 4 0 1
{
T 4200 4600 5  10 1 1 0 7 1 1
pinnumber=cpu0_we_o
T 4300 4600 5  10 0 1 0 7 1 1
pinseq=52
}
P 4300 4800 4600 4800 4 0 1
{
T 4200 4800 5  10 1 1 0 7 1 1
pinnumber=cpu0_stb_o
T 4300 4800 5  10 0 1 0 7 1 1
pinseq=53
}
P 4300 5000 4600 5000 4 0 1
{
T 4200 5000 5  10 1 1 0 7 1 1
pinnumber=cpu0_stall_o
T 4300 5000 5  10 0 1 0 7 1 1
pinseq=54
}
P 4300 5200 4600 5200 4 0 1
{
T 4200 5200 5  10 1 1 0 7 1 1
pinnumber=cpu0_rst_o
T 4300 5200 5  10 0 1 0 7 1 1
pinseq=55
}