Subversion Repositories socgen

v 20100214 1
B 300 0  4300 8100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 8250   5 10 1 1 0 0 1 1
device=io_module_def
T 400 8450 5 10 1 1 0 0 1 1
refdes=U?
T 400 8600    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 8600    0 10 0 1 0 0 1 1
library=io
T 400 8600    0 10 0 1 0 0 1 1
component=io_module
T 400 8600    0 10 0 1 0 0 1 1
version=def
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=vic_irq_in[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=reg_mb_wdata[7:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1 
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=reg_mb_addr[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1 
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=pic_irq_in[7:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1 
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=mem_wdata[15:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 10 1 1 
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=mem_addr[13:0]
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 10 1 1 
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=gpio_1_in[7:0]
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 10 1 1 
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=gpio_0_in[7:0]
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 10 1 1 
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=ext_rdata[15:0]
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 4 0 1  
{
T 400 2000 5 10 1 1 0 1 1 1 
pinnumber=uart_rxd_pad_in
T 400 2000 5 10 0 1 0 1 1 1 
pinseq=10
}
P 300 2200 0 2200 4 0 1  
{
T 400 2200 5 10 1 1 0 1 1 1 
pinnumber=reset
T 400 2200 5 10 0 1 0 1 1 1 
pinseq=11
}
P 300 2400 0 2400 4 0 1  
{
T 400 2400 5 10 1 1 0 1 1 1 
pinnumber=reg_mb_wr
T 400 2400 5 10 0 1 0 1 1 1 
pinseq=12
}
P 300 2600 0 2600 4 0 1  
{
T 400 2600 5 10 1 1 0 1 1 1 
pinnumber=reg_mb_rd
T 400 2600 5 10 0 1 0 1 1 1 
pinseq=13
}
P 300 2800 0 2800 4 0 1  
{
T 400 2800 5 10 1 1 0 1 1 1 
pinnumber=reg_mb_cs
T 400 2800 5 10 0 1 0 1 1 1 
pinseq=14
}
P 300 3000 0 3000 4 0 1  
{
T 400 3000 5 10 1 1 0 1 1 1 
pinnumber=ps2_data_pad_in
T 400 3000 5 10 0 1 0 1 1 1 
pinseq=15
}
P 300 3200 0 3200 4 0 1  
{
T 400 3200 5 10 1 1 0 1 1 1 
pinnumber=ps2_clk_pad_in
T 400 3200 5 10 0 1 0 1 1 1 
pinseq=16
}
P 300 3400 0 3400 4 0 1  
{
T 400 3400 5 10 1 1 0 1 1 1 
pinnumber=mem_wr
T 400 3400 5 10 0 1 0 1 1 1 
pinseq=17
}
P 300 3600 0 3600 4 0 1  
{
T 400 3600 5 10 1 1 0 1 1 1 
pinnumber=mem_rd
T 400 3600 5 10 0 1 0 1 1 1 
pinseq=18
}
P 300 3800 0 3800 4 0 1  
{
T 400 3800 5 10 1 1 0 1 1 1 
pinnumber=mem_cs
T 400 3800 5 10 0 1 0 1 1 1 
pinseq=19
}
P 300 4000 0 4000 4 0 1  
{
T 400 4000 5 10 1 1 0 1 1 1 
pinnumber=ext_wait
T 400 4000 5 10 0 1 0 1 1 1 
pinseq=20
}
P 300 4200 0 4200 4 0 1  
{
T 400 4200 5 10 1 1 0 1 1 1 
pinnumber=enable
T 400 4200 5 10 0 1 0 1 1 1 
pinseq=21
}
P 300 4400 0 4400 4 0 1  
{
T 400 4400 5 10 1 1 0 1 1 1 
pinnumber=cts_pad_in
T 400 4400 5 10 0 1 0 1 1 1 
pinseq=22
}
P 300 4600 0 4600 4 0 1  
{
T 400 4600 5 10 1 1 0 1 1 1 
pinnumber=clk
T 400 4600 5 10 0 1 0 1 1 1 
pinseq=23
}
P 4600 200 4900 200 10 1 1
{
T 4500 200 5  10 1 1 0 7 1 1 
pinnumber=y_pos[9:0]
T 4500 200 5  10 0 1 0 7 1 1 
pinseq=24
}
P 4600 400 4900 400 10 1 1
{
T 4500 400 5  10 1 1 0 7 1 1 
pinnumber=x_pos[9:0]
T 4500 400 5  10 0 1 0 7 1 1 
pinseq=25
}
P 4600 600 4900 600 10 1 1
{
T 4500 600 5  10 1 1 0 7 1 1 
pinnumber=vga_red_pad_out[2:0]
T 4500 600 5  10 0 1 0 7 1 1 
pinseq=26
}
P 4600 800 4900 800 10 1 1
{
T 4500 800 5  10 1 1 0 7 1 1 
pinnumber=vga_green_pad_out[2:0]
T 4500 800 5  10 0 1 0 7 1 1 
pinseq=27
}
P 4600 1000 4900 1000 10 1 1
{
T 4500 1000 5  10 1 1 0 7 1 1 
pinnumber=vga_blue_pad_out[1:0]
T 4500 1000 5  10 0 1 0 7 1 1 
pinseq=28
}
P 4600 1200 4900 1200 10 1 1
{
T 4500 1200 5  10 1 1 0 7 1 1 
pinnumber=vector[7:0]
T 4500 1200 5  10 0 1 0 7 1 1 
pinseq=29
}
P 4600 1400 4900 1400 10 1 1
{
T 4500 1400 5  10 1 1 0 7 1 1 
pinnumber=timer_irq[1:0]
T 4500 1400 5  10 0 1 0 7 1 1 
pinseq=30
}
P 4600 1600 4900 1600 10 1 1
{
T 4500 1600 5  10 1 1 0 7 1 1 
pinnumber=reg_mb_rdata[15:0]
T 4500 1600 5  10 0 1 0 7 1 1 
pinseq=31
}
P 4600 1800 4900 1800 10 1 1
{
T 4500 1800 5  10 1 1 0 7 1 1 
pinnumber=mem_rdata[15:0]
T 4500 1800 5  10 0 1 0 7 1 1 
pinseq=32
}
P 4600 2000 4900 2000 10 1 1
{
T 4500 2000 5  10 1 1 0 7 1 1 
pinnumber=gpio_1_out[7:0]
T 4500 2000 5  10 0 1 0 7 1 1 
pinseq=33
}
P 4600 2200 4900 2200 10 1 1
{
T 4500 2200 5  10 1 1 0 7 1 1 
pinnumber=gpio_1_oe[7:0]
T 4500 2200 5  10 0 1 0 7 1 1 
pinseq=34
}
P 4600 2400 4900 2400 10 1 1
{
T 4500 2400 5  10 1 1 0 7 1 1 
pinnumber=gpio_0_out[7:0]
T 4500 2400 5  10 0 1 0 7 1 1 
pinseq=35
}
P 4600 2600 4900 2600 10 1 1
{
T 4500 2600 5  10 1 1 0 7 1 1 
pinnumber=gpio_0_oe[7:0]
T 4500 2600 5  10 0 1 0 7 1 1 
pinseq=36
}
P 4600 2800 4900 2800 10 1 1
{
T 4500 2800 5  10 1 1 0 7 1 1 
pinnumber=ext_wdata[15:0]
T 4500 2800 5  10 0 1 0 7 1 1 
pinseq=37
}
P 4600 3000 4900 3000 10 1 1
{
T 4500 3000 5  10 1 1 0 7 1 1 
pinnumber=ext_cs[1:0]
T 4500 3000 5  10 0 1 0 7 1 1 
pinseq=38
}
P 4600 3200 4900 3200 10 1 1
{
T 4500 3200 5  10 1 1 0 7 1 1 
pinnumber=ext_addr[23:1]
T 4500 3200 5  10 0 1 0 7 1 1 
pinseq=39
}
P 4600 3400 4900 3400 4 0 1
{
T 4500 3400 5  10 1 1 0 7 1 1
pinnumber=vga_vsync_n_pad_out
T 4600 3400 5  10 0 1 0 7 1 1
pinseq=40
}
P 4600 3600 4900 3600 4 0 1
{
T 4500 3600 5  10 1 1 0 7 1 1
pinnumber=vga_hsync_n_pad_out
T 4600 3600 5  10 0 1 0 7 1 1
pinseq=41
}
P 4600 3800 4900 3800 4 0 1
{
T 4500 3800 5  10 1 1 0 7 1 1
pinnumber=uart_txd_pad_out
T 4600 3800 5  10 0 1 0 7 1 1
pinseq=42
}
P 4600 4000 4900 4000 4 0 1
{
T 4500 4000 5  10 1 1 0 7 1 1
pinnumber=tx_irq
T 4600 4000 5  10 0 1 0 7 1 1
pinseq=43
}
P 4600 4200 4900 4200 4 0 1
{
T 4500 4200 5  10 1 1 0 7 1 1
pinnumber=rx_irq
T 4600 4200 5  10 0 1 0 7 1 1
pinseq=44
}
P 4600 4400 4900 4400 4 0 1
{
T 4500 4400 5  10 1 1 0 7 1 1
pinnumber=rts_pad_out
T 4600 4400 5  10 0 1 0 7 1 1
pinseq=45
}
P 4600 4600 4900 4600 4 0 1
{
T 4500 4600 5  10 1 1 0 7 1 1
pinnumber=reg_mb_wait
T 4600 4600 5  10 0 1 0 7 1 1
pinseq=46
}
P 4600 4800 4900 4800 4 0 1
{
T 4500 4800 5  10 1 1 0 7 1 1
pinnumber=ps2_data_pad_oe
T 4600 4800 5  10 0 1 0 7 1 1
pinseq=47
}
P 4600 5000 4900 5000 4 0 1
{
T 4500 5000 5  10 1 1 0 7 1 1
pinnumber=ps2_data_avail
T 4600 5000 5  10 0 1 0 7 1 1
pinseq=48
}
P 4600 5200 4900 5200 4 0 1
{
T 4500 5200 5  10 1 1 0 7 1 1
pinnumber=ps2_clk_pad_oe
T 4600 5200 5  10 0 1 0 7 1 1
pinseq=49
}
P 4600 5400 4900 5400 4 0 1
{
T 4500 5400 5  10 1 1 0 7 1 1
pinnumber=pic_nmi
T 4600 5400 5  10 0 1 0 7 1 1
pinseq=50
}
P 4600 5600 4900 5600 4 0 1
{
T 4500 5600 5  10 1 1 0 7 1 1
pinnumber=pic_irq
T 4600 5600 5  10 0 1 0 7 1 1
pinseq=51
}
P 4600 5800 4900 5800 4 0 1
{
T 4500 5800 5  10 1 1 0 7 1 1
pinnumber=new_packet
T 4600 5800 5  10 0 1 0 7 1 1
pinseq=52
}
P 4600 6000 4900 6000 4 0 1
{
T 4500 6000 5  10 1 1 0 7 1 1
pinnumber=ms_right
T 4600 6000 5  10 0 1 0 7 1 1
pinseq=53
}
P 4600 6200 4900 6200 4 0 1
{
T 4500 6200 5  10 1 1 0 7 1 1
pinnumber=ms_mid
T 4600 6200 5  10 0 1 0 7 1 1
pinseq=54
}
P 4600 6400 4900 6400 4 0 1
{
T 4500 6400 5  10 1 1 0 7 1 1
pinnumber=ms_left
T 4600 6400 5  10 0 1 0 7 1 1
pinseq=55
}
P 4600 6600 4900 6600 4 0 1
{
T 4500 6600 5  10 1 1 0 7 1 1
pinnumber=mem_wait
T 4600 6600 5  10 0 1 0 7 1 1
pinseq=56
}
P 4600 6800 4900 6800 4 0 1
{
T 4500 6800 5  10 1 1 0 7 1 1
pinnumber=int_out
T 4600 6800 5  10 0 1 0 7 1 1
pinseq=57
}
P 4600 7000 4900 7000 4 0 1
{
T 4500 7000 5  10 1 1 0 7 1 1
pinnumber=ext_wr
T 4600 7000 5  10 0 1 0 7 1 1
pinseq=58
}
P 4600 7200 4900 7200 4 0 1
{
T 4500 7200 5  10 1 1 0 7 1 1
pinnumber=ext_ub
T 4600 7200 5  10 0 1 0 7 1 1
pinseq=59
}
P 4600 7400 4900 7400 4 0 1
{
T 4500 7400 5  10 1 1 0 7 1 1
pinnumber=ext_stb
T 4600 7400 5  10 0 1 0 7 1 1
pinseq=60
}
P 4600 7600 4900 7600 4 0 1
{
T 4500 7600 5  10 1 1 0 7 1 1
pinnumber=ext_rd
T 4600 7600 5  10 0 1 0 7 1 1
pinseq=61
}
P 4600 7800 4900 7800 4 0 1
{
T 4500 7800 5  10 1 1 0 7 1 1
pinnumber=ext_lb
T 4600 7800 5  10 0 1 0 7 1 1
pinseq=62
}