Subversion Repositories socgen

v 20100214 1
B 300 0  3900 3100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 3250   5 10 1 1 0 0 1 1
device=io_module_gpio
T 400 3450 5 10 1 1 0 0 1 1
refdes=U?
T 400 3600    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 3600    0 10 0 1 0 0 1 1
library=io
T 400 3600    0 10 0 1 0 0 1 1
component=io_module
T 400 3600    0 10 0 1 0 0 1 1
version=gpio
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=reg_mb_wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=reg_mb_addr[7:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1 
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=pic_irq_in[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1 
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=gpio_1_in[7:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1 
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=gpio_0_in[7:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1  
{
T 400 1200 5 10 1 1 0 1 1 1 
pinnumber=uart_rxd_pad_in
T 400 1200 5 10 0 1 0 1 1 1 
pinseq=6
}
P 300 1400 0 1400 4 0 1  
{
T 400 1400 5 10 1 1 0 1 1 1 
pinnumber=reset
T 400 1400 5 10 0 1 0 1 1 1 
pinseq=7
}
P 300 1600 0 1600 4 0 1  
{
T 400 1600 5 10 1 1 0 1 1 1 
pinnumber=reg_mb_wr
T 400 1600 5 10 0 1 0 1 1 1 
pinseq=8
}
P 300 1800 0 1800 4 0 1  
{
T 400 1800 5 10 1 1 0 1 1 1 
pinnumber=reg_mb_rd
T 400 1800 5 10 0 1 0 1 1 1 
pinseq=9
}
P 300 2000 0 2000 4 0 1  
{
T 400 2000 5 10 1 1 0 1 1 1 
pinnumber=reg_mb_cs
T 400 2000 5 10 0 1 0 1 1 1 
pinseq=10
}
P 300 2200 0 2200 4 0 1  
{
T 400 2200 5 10 1 1 0 1 1 1 
pinnumber=enable
T 400 2200 5 10 0 1 0 1 1 1 
pinseq=11
}
P 300 2400 0 2400 4 0 1  
{
T 400 2400 5 10 1 1 0 1 1 1 
pinnumber=cts_pad_in
T 400 2400 5 10 0 1 0 1 1 1 
pinseq=12
}
P 300 2600 0 2600 4 0 1  
{
T 400 2600 5 10 1 1 0 1 1 1 
pinnumber=clk
T 400 2600 5 10 0 1 0 1 1 1 
pinseq=13
}
P 4200 200 4500 200 10 1 1
{
T 4100 200 5  10 1 1 0 7 1 1 
pinnumber=timer_irq[1:0]
T 4100 200 5  10 0 1 0 7 1 1 
pinseq=14
}
P 4200 400 4500 400 10 1 1
{
T 4100 400 5  10 1 1 0 7 1 1 
pinnumber=reg_mb_rdata[15:0]
T 4100 400 5  10 0 1 0 7 1 1 
pinseq=15
}
P 4200 600 4500 600 10 1 1
{
T 4100 600 5  10 1 1 0 7 1 1 
pinnumber=gpio_1_out[7:0]
T 4100 600 5  10 0 1 0 7 1 1 
pinseq=16
}
P 4200 800 4500 800 10 1 1
{
T 4100 800 5  10 1 1 0 7 1 1 
pinnumber=gpio_1_oe[7:0]
T 4100 800 5  10 0 1 0 7 1 1 
pinseq=17
}
P 4200 1000 4500 1000 10 1 1
{
T 4100 1000 5  10 1 1 0 7 1 1 
pinnumber=gpio_0_out[7:0]
T 4100 1000 5  10 0 1 0 7 1 1 
pinseq=18
}
P 4200 1200 4500 1200 10 1 1
{
T 4100 1200 5  10 1 1 0 7 1 1 
pinnumber=gpio_0_oe[7:0]
T 4100 1200 5  10 0 1 0 7 1 1 
pinseq=19
}
P 4200 1400 4500 1400 4 0 1
{
T 4100 1400 5  10 1 1 0 7 1 1
pinnumber=wait_n
T 4200 1400 5  10 0 1 0 7 1 1
pinseq=20
}
P 4200 1600 4500 1600 4 0 1
{
T 4100 1600 5  10 1 1 0 7 1 1
pinnumber=uart_txd_pad_out
T 4200 1600 5  10 0 1 0 7 1 1
pinseq=21
}
P 4200 1800 4500 1800 4 0 1
{
T 4100 1800 5  10 1 1 0 7 1 1
pinnumber=tx_irq
T 4200 1800 5  10 0 1 0 7 1 1
pinseq=22
}
P 4200 2000 4500 2000 4 0 1
{
T 4100 2000 5  10 1 1 0 7 1 1
pinnumber=rx_irq
T 4200 2000 5  10 0 1 0 7 1 1
pinseq=23
}
P 4200 2200 4500 2200 4 0 1
{
T 4100 2200 5  10 1 1 0 7 1 1
pinnumber=rts_pad_out
T 4200 2200 5  10 0 1 0 7 1 1
pinseq=24
}
P 4200 2400 4500 2400 4 0 1
{
T 4100 2400 5  10 1 1 0 7 1 1
pinnumber=reg_mb_wait
T 4200 2400 5  10 0 1 0 7 1 1
pinseq=25
}
P 4200 2600 4500 2600 4 0 1
{
T 4100 2600 5  10 1 1 0 7 1 1
pinnumber=pic_nmi
T 4200 2600 5  10 0 1 0 7 1 1
pinseq=26
}
P 4200 2800 4500 2800 4 0 1
{
T 4100 2800 5  10 1 1 0 7 1 1
pinnumber=pic_irq
T 4200 2800 5  10 0 1 0 7 1 1
pinseq=27
}