Subversion Repositories socgen

v 20100214 1
C 2600 300 1 0 0 in_port_vector.sym   
{
T 2600 300 5 10 1 1 0 6 1 1
refdes=sw_pad_in[7:0]
}
C 2600 700 1 0 0 in_port_vector.sym   
{
T 2600 700 5 10 1 1 0 6 1 1
refdes=btn_pad_in[3:0]
}
C 2600 1100 1 0 0 in_port_vector.sym   
{
T 2600 1100 5 10 1 1 0 6 1 1
refdes=PosL[7:0]
}
C 2600 1500 1 0 0 in_port_vector.sym   
{
T 2600 1500 5 10 1 1 0 6 1 1
refdes=PosD[15:0]
}
C 2600 1900 1 0 0 in_port.sym  
{
T 2600 1900 5 10 1 1 0 6 1 1 
refdes=reset
}
C 2600 2300 1 0 0 in_port.sym  
{
T 2600 2300 5 10 1 1 0 6 1 1 
refdes=jtag_update_dr_clk
}
C 2600 2700 1 0 0 in_port.sym  
{
T 2600 2700 5 10 1 1 0 6 1 1 
refdes=jtag_test_logic_reset
}
C 2600 3100 1 0 0 in_port.sym  
{
T 2600 3100 5 10 1 1 0 6 1 1 
refdes=jtag_tdi
}
C 2600 3500 1 0 0 in_port.sym  
{
T 2600 3500 5 10 1 1 0 6 1 1 
refdes=jtag_shiftcapture_dr_clk
}
C 2600 3900 1 0 0 in_port.sym  
{
T 2600 3900 5 10 1 1 0 6 1 1 
refdes=jtag_shift_dr
}
C 2600 4300 1 0 0 in_port.sym  
{
T 2600 4300 5 10 1 1 0 6 1 1 
refdes=jtag_select
}
C 2600 4700 1 0 0 in_port.sym  
{
T 2600 4700 5 10 1 1 0 6 1 1 
refdes=jtag_capture_dr
}
C 2600 5100 1 0 0 in_port.sym  
{
T 2600 5100 5 10 1 1 0 6 1 1 
refdes=enable
}
C 2600 5500 1 0 0 in_port.sym  
{
T 2600 5500 5 10 1 1 0 6 1 1 
refdes=clk
}
C 5500 300  1 0  0 out_port_vector.sym
{
T 6500 300 5  10 1 1 0 0 1 1 
refdes=seg_pad_out[6:0]
}
C 5500 700  1 0  0 out_port_vector.sym
{
T 6500 700 5  10 1 1 0 0 1 1 
refdes=led_pad_out[7:0]
}
C 5500 1100  1 0  0 out_port_vector.sym
{
T 6500 1100 5  10 1 1 0 0 1 1 
refdes=an_pad_out[3:0]
}
C 5500 1500  1 0  0 out_port_vector.sym
{
T 6500 1500 5  10 1 1 0 0 1 1 
refdes=PosS[7:0]
}
C 5500 1900  1 0  0 out_port_vector.sym
{
T 6500 1900 5  10 1 1 0 0 1 1 
refdes=PosB[3:0]
}
C 5500 2300  1 0 0 out_port.sym
{
T 6500 2300 5  10 1 1 0 0 1 1
refdes=jtag_tdo
}
C 5500 2700  1 0 0 out_port.sym
{
T 6500 2700 5  10 1 1 0 0 1 1
refdes=dp_pad_out
}