Subversion Repositories socgen

v 20100214 1
B 300 0  5800 2900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 3050   5 10 1 1 0 0 1 1
device=wb_uart16550_def
T 400 3250 5 10 1 1 0 0 1 1
refdes=U?
T 400 3400    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 3400    0 10 0 1 0 0 1 1
library=wishbone
T 400 3400    0 10 0 1 0 0 1 1
component=wb_uart16550
T 400 3400    0 10 0 1 0 0 1 1
version=def
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wb_dat_i[WB_DATA_WIDTH-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=wb_adr_i[WB_ADDR_WIDTH-1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1  
{
T 400 600 5 10 1 1 0 1 1 1 
pinnumber=wb_we_i
T 400 600 5 10 0 1 0 1 1 1 
pinseq=3
}
P 300 800 0 800 4 0 1  
{
T 400 800 5 10 1 1 0 1 1 1 
pinnumber=wb_stb_i
T 400 800 5 10 0 1 0 1 1 1 
pinseq=4
}
P 300 1000 0 1000 4 0 1  
{
T 400 1000 5 10 1 1 0 1 1 1 
pinnumber=wb_sel_i
T 400 1000 5 10 0 1 0 1 1 1 
pinseq=5
}
P 300 1200 0 1200 4 0 1  
{
T 400 1200 5 10 1 1 0 1 1 1 
pinnumber=wb_rst_i
T 400 1200 5 10 0 1 0 1 1 1 
pinseq=6
}
P 300 1400 0 1400 4 0 1  
{
T 400 1400 5 10 1 1 0 1 1 1 
pinnumber=wb_cyc_i
T 400 1400 5 10 0 1 0 1 1 1 
pinseq=7
}
P 300 1600 0 1600 4 0 1  
{
T 400 1600 5 10 1 1 0 1 1 1 
pinnumber=wb_clk_i
T 400 1600 5 10 0 1 0 1 1 1 
pinseq=8
}
P 300 1800 0 1800 4 0 1  
{
T 400 1800 5 10 1 1 0 1 1 1 
pinnumber=srx_pad_i
T 400 1800 5 10 0 1 0 1 1 1 
pinseq=9
}
P 300 2000 0 2000 4 0 1  
{
T 400 2000 5 10 1 1 0 1 1 1 
pinnumber=ri_pad_i
T 400 2000 5 10 0 1 0 1 1 1 
pinseq=10
}
P 300 2200 0 2200 4 0 1  
{
T 400 2200 5 10 1 1 0 1 1 1 
pinnumber=dsr_pad_i
T 400 2200 5 10 0 1 0 1 1 1 
pinseq=11
}
P 300 2400 0 2400 4 0 1  
{
T 400 2400 5 10 1 1 0 1 1 1 
pinnumber=dcd_pad_i
T 400 2400 5 10 0 1 0 1 1 1 
pinseq=12
}
P 300 2600 0 2600 4 0 1  
{
T 400 2600 5 10 1 1 0 1 1 1 
pinnumber=cts_pad_i
T 400 2600 5 10 0 1 0 1 1 1 
pinseq=13
}
P 6100 200 6400 200 10 1 1
{
T 6000 200 5  10 1 1 0 7 1 1 
pinnumber=wb_dat_o[WB_DATA_WIDTH-1:0]
T 6000 200 5  10 0 1 0 7 1 1 
pinseq=14
}
P 6100 400 6400 400 4 0 1
{
T 6000 400 5  10 1 1 0 7 1 1
pinnumber=wb_ack_o
T 6100 400 5  10 0 1 0 7 1 1
pinseq=15
}
P 6100 600 6400 600 4 0 1
{
T 6000 600 5  10 1 1 0 7 1 1
pinnumber=stx_pad_o
T 6100 600 5  10 0 1 0 7 1 1
pinseq=16
}
P 6100 800 6400 800 4 0 1
{
T 6000 800 5  10 1 1 0 7 1 1
pinnumber=rts_pad_o
T 6100 800 5  10 0 1 0 7 1 1
pinseq=17
}
P 6100 1000 6400 1000 4 0 1
{
T 6000 1000 5  10 1 1 0 7 1 1
pinnumber=int_o
T 6100 1000 5  10 0 1 0 7 1 1
pinseq=18
}
P 6100 1200 6400 1200 4 0 1
{
T 6000 1200 5  10 1 1 0 7 1 1
pinnumber=dtr_pad_o
T 6100 1200 5  10 0 1 0 7 1 1
pinseq=19
}
P 6100 1400 6400 1400 4 0 1
{
T 6000 1400 5  10 1 1 0 7 1 1
pinnumber=baud_o
T 6100 1400 5  10 0 1 0 7 1 1
pinseq=20
}