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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.design.xml] - Rev 135

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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<ipxact:design 
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

<ipxact:vendor>valentfx.com</ipxact:vendor>
<ipxact:library>fpgas</ipxact:library>
<ipxact:name>logipi_T6502</ipxact:name>
<ipxact:version>core.design</ipxact:version>  








  <ipxact:interconnections>



  <ipxact:interconnection>
      <ipxact:name>jtag</ipxact:name>
       <ipxact:activeInterface componentRef="jtag_rpc1" busRef="jtag"></ipxact:activeInterface>
    <ipxact:hierInterface busRef="jtag"/>
  </ipxact:interconnection>


    <ipxact:interconnection>
      <ipxact:name>aux_jtag</ipxact:name>
       <ipxact:activeInterface componentRef="jtag_rpc2" busRef="jtag"></ipxact:activeInterface>
    <ipxact:hierInterface busRef="aux_jtag"/>
    </ipxact:interconnection>   
    
        

  </ipxact:interconnections>







  <ipxact:adHocConnections>

    <ipxact:adHocConnection>
      <ipxact:name>clk</ipxact:name>
      <ipxact:externalPortReference portRef="slave_clk_clk"/>
      <ipxact:internalPortReference componentRef="spi_xxx" portRef="clk" />
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>reset</ipxact:name>
      <ipxact:externalPortReference portRef="slave_reset_reset"/>
      <ipxact:internalPortReference componentRef="spi_xxx" portRef="reset" />
    </ipxact:adHocConnection>



    <ipxact:adHocConnection>
      <ipxact:name>btn_pad_in</ipxact:name>
      <ipxact:externalPortReference portRef="btn_pad_pad_in"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>sw_pad_in</ipxact:name>
      <ipxact:externalPortReference portRef="sw_pad_pad_in"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>led_pad_out</ipxact:name>
      <ipxact:externalPortReference portRef="led_pad_pad_out"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>sys_spi_sck_pad_in</ipxact:name>
      <ipxact:externalPortReference portRef="sys_spi_sck_pad_pad_in"/>
      <ipxact:internalPortReference componentRef="spi_xxx" portRef="spi_clk_pad_in" />
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>sys_spi_mosi_pad_in</ipxact:name>
      <ipxact:externalPortReference portRef="sys_spi_mosi_pad_pad_in"/>
      <ipxact:internalPortReference componentRef="spi_xxx" portRef="spi_mosi_pad_in" />
    </ipxact:adHocConnection>



    <ipxact:adHocConnection>
      <ipxact:name>sys_spi_miso_pad_out</ipxact:name>
      <ipxact:externalPortReference portRef="sys_spi_miso_pad_pad_out"/>
      <ipxact:internalPortReference componentRef="spi_xxx" portRef="spi_miso_pad_out" />
    </ipxact:adHocConnection>


    
    <ipxact:adHocConnection>
      <ipxact:name>rp_spi_ce0n_pad_in</ipxact:name>
      <ipxact:externalPortReference portRef="rp_spi_ce0n_pad_pad_in"/>
      <ipxact:internalPortReference componentRef="spi_xxx" portRef="spi_sel_n_pad_in" />
    </ipxact:adHocConnection>


        
<ipxact:adHocConnection>
<ipxact:name>tx_data</ipxact:name>
<ipxact:externalPortReference portRef="tx_data"  left="15"    right="0"/>
<ipxact:internalPortReference componentRef="spi_xxx" portRef="tx_data" />
</ipxact:adHocConnection>


<ipxact:adHocConnection>
<ipxact:name>rx_data</ipxact:name>
<ipxact:externalPortReference portRef="rx_data"  left="15"    right="0"/>
<ipxact:internalPortReference componentRef="spi_xxx" portRef="rx_data" />
</ipxact:adHocConnection>





    
<ipxact:adHocConnection>
<ipxact:name>pmod3_pad_out</ipxact:name>
<ipxact:externalPortReference portRef="update_value"  left="7"    right="0"/>
<ipxact:internalPortReference componentRef="jtag_rpc1" portRef="update_value" />
<ipxact:internalPortReference componentRef="jtag_rpc1" portRef="capture_value" />
</ipxact:adHocConnection>


<ipxact:adHocConnection>
<ipxact:name>pmod4_pad_out</ipxact:name>
<ipxact:externalPortReference portRef="update_value"  left="7"    right="0"/>
<ipxact:internalPortReference componentRef="jtag_rpc2" portRef="update_value" />
<ipxact:internalPortReference componentRef="jtag_rpc2" portRef="capture_value" />
</ipxact:adHocConnection>







</ipxact:adHocConnections>




<ipxact:componentInstances>


<ipxact:componentInstance>
 <ipxact:instanceName>jtag_rpc1</ipxact:instanceName> <ipxact:componentRef vendor="opencores.org" library="cde" name="jtag" version="classic_rpc_reg" />
 <ipxact:configurableElementValues>
 <ipxact:configurableElementValue referenceId="BITS">8</ipxact:configurableElementValue>
 <ipxact:configurableElementValue referenceId="RESET_VALUE">8'haa</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>



<ipxact:componentInstance>
 <ipxact:instanceName>jtag_rpc2</ipxact:instanceName> <ipxact:componentRef vendor="opencores.org" library="cde" name="jtag" version="classic_rpc_reg" />
 <ipxact:configurableElementValues>
 <ipxact:configurableElementValue referenceId="BITS">8</ipxact:configurableElementValue>
 <ipxact:configurableElementValue referenceId="RESET_VALUE">8'h55</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>

<ipxact:componentInstance>
<ipxact:instanceName>spi_xxx</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="logic" name="spi_interface" version="def" />
<ipxact:configurableElementValues>
</ipxact:configurableElementValues>
</ipxact:componentInstance>






</ipxact:componentInstances>













</ipxact:design>



   


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