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[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [INV/] [not.sym] - Rev 135

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v 20031231 1
L 300 800 800 500 3 0 0 0 -1 -1
L 800 500 300 200 3 0 0 0 -1 -1
L 300 800 300 500 3 0 0 0 -1 -1
L 300 500 300 200 3 0 0 0 -1 -1
V 850 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 1100 500 900 500 1 0 0
{
T 915 550 5 8 0 1 0 0 1
pinnumber=OUT
T 915 550 5 8 0 0 0 0 1
pinseq=1
}
P 300 500 0 500 1 0 1
{
T 100 550 5 8 0 1 0 0 1
pinnumber=IN
T 100 550 5 8 0 0 0 0 1
pinseq=2
}
T 200 900 2 10 0 0 0 0 1
VERILOG_PORTS=POSITIONAL
T 200 1000 2 10 0 0 0 0 1
device=not
T 500 300 5 10 1 1 0 2 1
refdes=U?

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