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[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [NOR/] [nor3.sym] - Rev 135

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v 20031231 1
L 300 600 600 600 3 0 0 0 -1 -1
L 300 0 600 0 3 0 0 0 -1 -1
A 40 300 400 312 97 3 0 0 0 -1 -1
A 600 400 400 270 76 3 0 0 0 -1 -1
A 600 200 400 14 76 3 0 0 0 -1 -1
V 1050 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 1100 300 1300 300 1 0 1
{
T 1000 300 5 8 0 0 0 0 1
pinnumber=OUT
T 1000 300 5 8 0 0 0 0 1
pinseq=1
}
P 300 100 0 100 1 0 1
{
T 300 100 5 8 0 0 0 0 1
pinnumber=IN0
T 300 100 5 8 0 0 0 0 1
pinseq=2
}
P 300 300 0 300 1 0 1
{
T 300 300 5 8 0 0 0 0 1
pinnumber=IN1
T 300 300 5 8 0 0 0 0 1
pinseq=3
}
P 300 500 0 500 1 0 1
{
T 300 500 5 8 0 0 0 0 1
pinnumber=IN2
T 300 500 5 8 0 0 0 0 1
pinseq=4
}
T 400 -100 5 10 1 1 0 2 1
refdes=U?
T 400 100 5 8 0 0 0 0 1
device=nor
T 400 200 5 8 0 0 0 0 1
VERILOG_PORTS=POSITIONAL

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