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[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [OR/] [or4.sym] - Rev 135

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v 20031231 1
L 300 700 600 700 3 0 0 0 -1 -1
L 300 100 600 100 3 0 0 0 -1 -1
A 40 400 400 312 97 3 0 0 0 -1 -1
A 600 500 400 270 76 3 0 0 0 -1 -1
A 600 300 400 14 76 3 0 0 0 -1 -1
L 300 700 300 800 3 0 0 0 -1 -1
L 300 100 300 0 3 0 0 0 -1 -1
P 1000 400 1300 400 1 0 1
{
T 1000 400 5 8 0 0 0 0 1
pinnumber=OUT
T 1000 400 5 8 0 0 0 0 1
pinseq=1
}
P 300 100 0 100 1 0 1
{
T 300 100 5 8 0 0 0 0 1
pinnumber=IN0
T 300 100 5 8 0 0 0 0 1
pinseq=2
}
P 300 300 0 300 1 0 1
{
T 300 300 5 8 0 0 0 0 1
pinnumber=IN1
T 300 300 5 8 0 0 0 0 1
pinseq=3
}
P 300 500 0 500 1 0 1
{
T 300 500 5 8 0 0 0 0 1
pinnumber=IN2
T 300 500 5 8 0 0 0 0 1
pinseq=4
}
P 300 700 0 700 1 0 1
{
T 300 700 5 8 0 0 0 0 1
pinnumber=IN3
T 300 700 5 8 0 0 0 0 1
pinseq=5
}
T 400 0 5 10 1 1 0 2 1
refdes=U?
T 400 100 5 8 0 0 0 0 1
device=or
T 400 200 5 8 0 0 0 0 1
VERILOG_PORTS=POSITIONAL

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