Subversion Repositories socgen

module spi_host_def 
 
(
input  wire         clk,
input  wire         reset, 
input  wire         busy,
 
input  wire [7:0]   rx_data,               
input  wire         rx_read,               
input  wire         rx_full,               
input  wire         rx_parity_error,       
input  wire         rx_parity_rcv,         
input  wire         rx_parity_cal,         
input  wire         rx_frame_error,        
inout  wire         tx_ack_error,          
 
output  reg         rx_clr,           
output reg [7:0]    tx_data,               
output reg          tx_write 
);
 
 
reg                 exp_tx_ack_err;
reg                 mask_tx_ack_err;
 
reg   [7:0]         exp_rcv_byte;
reg   [7:0]         mask_rcv_byte;
 
 
always@(posedge clk)
  if(reset)
    begin
    tx_data              <= 8'h00;
    tx_write             <= 1'b0;
    rx_clr               <= 1'b0;
    exp_tx_ack_err       <= 1'b0;
    mask_tx_ack_err      <= 1'b0;
    exp_rcv_byte         <= 8'h00;
    mask_rcv_byte        <= 8'h00;       
 end
 
 
 
 
 
 
 
endmodule