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<?xml version="1.0" encoding="UTF-8"?><!-- edited with XMLSpy v2013 sp1 (http://www.altova.com) by Mark Noll (private) --><!--// Description : busInterface.xsd// Author: The Accellera System Initiative IP-XACT Schema Working Group//// Revision: $Revision: 1537 $// Date: $Date: 2010-02-26 13:28:40 -0800 (Fri, 26 Feb 2010) $//// Copyright (c) 2005 - 2012 Accellera Systems Initiative Inc.// All rights reserved.//// This source file is provided on an AS IS basis. The Accellera// Systems Initiative disclaims any warranty express or implied// including any warranty of merchantability and fitness for use// for a particular purpose.//// The user of the source file shall indemnify and hold The Accellera// Systems Initiative and its members harmless from any damages or liability.//// This file may be copied, and distributed, WITHOUT// modifications; this notice must be included on any copy.//// This schema shall not be modified, adapted, altered, sublicensed, nor// any derivative works shall be created based upon the schema. The// intended and allowed uses of the schema include://// o Creating and validating XML documents that conform to the schema//// o Building software programs and systems based on the schema//// o Distributing verbatim copy of the schema as long as the full text// of this license is included in all copies of the schema.// Specifically, a tool may include full copies of the schema, and these// copies may be distributed by the tool provider directly. A link or// URL to the original of the schema is inherent in the schema URI.//// o Documents which are validated against this schema may also// reference additional schema. These additional schemas may provide for// validation of elements and attributes at the extension points// explicitly and implicitly included in the IEEE 1685-???? standard.//// o No right to create new schemas derived from parts of this base// schema is granted pursuant to this License.//// Users are requested to provide feedback to The Accellera Systems// Initiative IP-XACT Schema Working Group using:// mailto:ip-xact-swg@lists.accellera.org--><xs:schema xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" xmlns:xs="http://www.w3.org/2001/XMLSchema" targetNamespace="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" elementFormDefault="qualified"><xs:include schemaLocation="abstractionDefinition.xsd"/><xs:include schemaLocation="identifier.xsd"/><xs:include schemaLocation="memoryMap.xsd"/><xs:include schemaLocation="port.xsd"/><xs:include schemaLocation="autoConfigure.xsd"/><xs:complexType name="complexBitSteeringExpression"><xs:annotation><xs:documentation>Indicates whether bit steering should be used to map this interface onto a bus of different data width.Values are "on", "off" or an expression which resolves to an unsigned-bit where a '1' indicates "on" and a '0' indicates "off" (defaults to "off").</xs:documentation></xs:annotation><xs:simpleContent><xs:extension base="ipxact:simpleBitSteeringExpression"><xs:attributeGroup ref="ipxact:any.att"/></xs:extension></xs:simpleContent></xs:complexType><xs:simpleType name="simpleBitSteeringExpression"><xs:annotation><xs:documentation>Indicates whether bit steering should be used to map this interface onto a bus of different data width.Values are "on", "off" (defaults to "off").</xs:documentation></xs:annotation><xs:restriction><xs:simpleType><xs:union memberTypes="ipxact:simpleUnsignedBitExpression"><xs:simpleType><xs:restriction base="xs:string"><xs:enumeration value="on"/><xs:enumeration value="off"/></xs:restriction></xs:simpleType></xs:union></xs:simpleType></xs:restriction></xs:simpleType><xs:simpleType name="endianessType"><xs:annotation><xs:documentation>'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian.</xs:documentation></xs:annotation><xs:restriction base="xs:string"><xs:enumeration value="big"/><xs:enumeration value="little"/></xs:restriction></xs:simpleType><xs:element name="bitsInLau" type="ipxact:unsignedPositiveLongintExpression"><xs:annotation><xs:documentation>The number of bits in the least addressable unit. The default is byte addressable (8 bits).</xs:documentation></xs:annotation></xs:element><xs:element name="viewRef"><xs:complexType><xs:simpleContent><xs:extension base="xs:NMTOKEN"><xs:attributeGroup ref="ipxact:id.att"/></xs:extension></xs:simpleContent></xs:complexType></xs:element><xs:element name="busInterface" type="ipxact:busInterfaceType"><xs:annotation><xs:documentation>Describes one of the bus interfaces supported by this component.</xs:documentation></xs:annotation></xs:element><xs:element name="busInterfaces"><xs:annotation><xs:documentation>A list of bus interfaces supported by this component.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:busInterface" maxOccurs="unbounded"/></xs:sequence></xs:complexType></xs:element><xs:complexType name="busInterfaceType"><xs:annotation><xs:documentation>Type definition for a busInterface in a component</xs:documentation></xs:annotation><xs:sequence><xs:group ref="ipxact:nameGroup"/><xs:element ref="ipxact:isPresent" minOccurs="0"/><xs:element name="busType" type="ipxact:configurableLibraryRefType"><xs:annotation><xs:documentation>The bus type of this interface. Refers to bus definition using vendor, library, name, version attributes along with any configurable element values needed to configure this interface.</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:abstractionTypes" minOccurs="0"/><xs:group ref="ipxact:interfaceMode"><xs:annotation><xs:documentation>Indicates the usage mode of this instance of the bus interface.</xs:documentation></xs:annotation></xs:group><xs:element name="connectionRequired" type="xs:boolean" default="false" minOccurs="0"><xs:annotation><xs:documentation>Indicates whether a connection to this interface is required for proper component functionality.</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:bitsInLau" minOccurs="0"/><xs:element name="bitSteering" type="ipxact:complexBitSteeringExpression" default="off" minOccurs="0"><xs:annotation><xs:documentation>Indicates whether bit steering should be used to map this interface onto a bus of different data width.Values are "on", "off" (defaults to "off").</xs:documentation></xs:annotation></xs:element><xs:element name="endianness" type="ipxact:endianessType" minOccurs="0"><xs:annotation><xs:documentation>'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian.</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:parameters" minOccurs="0"/><xs:element ref="ipxact:vendorExtensions" minOccurs="0"/></xs:sequence><xs:attributeGroup ref="ipxact:any.att"/></xs:complexType><xs:element name="group" type="xs:Name"><xs:annotation><xs:documentation>Indicates which system interface is being mirrored. Name must match a group name present on one or more ports in the corresonding bus definition.</xs:documentation></xs:annotation></xs:element><xs:element name="channels"><xs:annotation><xs:documentation>Lists all channel connections between mirror interfaces of this component.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="channel" maxOccurs="unbounded"><xs:annotation><xs:documentation>Defines a set of mirrored interfaces of this component that are connected to one another.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:group ref="ipxact:nameGroup"/><xs:element ref="ipxact:isPresent" minOccurs="0"/><xs:element name="busInterfaceRef" minOccurs="2" maxOccurs="unbounded"><xs:annotation><xs:documentation>Contains the name of one of the bus interfaces that is part of this channel. The ordering of the references may be important to the design environment.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="localName" type="xs:Name"/><xs:element ref="ipxact:isPresent" minOccurs="0"/></xs:sequence><xs:attributeGroup ref="ipxact:id.att"/></xs:complexType></xs:element></xs:sequence><xs:attributeGroup ref="ipxact:id.att"/></xs:complexType></xs:element></xs:sequence></xs:complexType><xs:unique name="channelConnections"><xs:selector xpath="ipxact:channel/ipxact:busInterfaceRef/ipxact:localName"/><xs:field xpath="."/></xs:unique></xs:element><xs:element name="remapStates"><xs:annotation><xs:documentation>Contains a list of remap state names and associated port values</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="remapState" maxOccurs="unbounded"><xs:annotation><xs:documentation>Contains a list of ports and values in remapPort and a list of registers and values that when all evaluate to true which tell the decoder to enter this remap state. The name attribute identifies the name of the state. If a list of remapPorts and/or remapRegisters is not defined then the condition for that state cannot be defined.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:group ref="ipxact:nameGroup"/><xs:element name="remapPorts" minOccurs="0"><xs:annotation><xs:documentation>List of ports and their values that shall invoke this remap state.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="remapPort" maxOccurs="unbounded"><xs:annotation><xs:documentation>Contains the name and value of a port on the component, the value indicates the logic value which this port must take to effect the remapping. The portMapRef attribute stores the name of the port which takes that value.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="portIndex" type="ipxact:unsignedIntExpression" minOccurs="0"><xs:annotation><xs:documentation>Index for a vectored type port. Must be a number between left and right for the port.</xs:documentation></xs:annotation></xs:element><xs:element name="value" type="ipxact:unsignedIntExpression"/></xs:sequence><xs:attribute name="portRef" type="ipxact:portName" use="required"><xs:annotation><xs:documentation>This attribute identifies a signal on the component which affects the component's memory layout </xs:documentation></xs:annotation></xs:attribute></xs:complexType></xs:element></xs:sequence></xs:complexType></xs:element></xs:sequence></xs:complexType></xs:element></xs:sequence></xs:complexType></xs:element><xs:group name="interfaceMode"><xs:annotation><xs:documentation>Group of the different modes a busInterface can take on in a component</xs:documentation></xs:annotation><xs:choice><xs:element name="master"><xs:annotation><xs:documentation>If this element is present, the bus interface can serve as a master. This element encapsulates additional information related to its role as master.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="addressSpaceRef" minOccurs="0"><xs:annotation><xs:documentation>If this master connects to an addressable bus, this element references the address space it maps to.</xs:documentation></xs:annotation><xs:complexType><xs:complexContent><xs:extension base="ipxact:addrSpaceRefType"><xs:sequence><xs:annotation><xs:documentation>If the master's mapping to the physical address space is not zero based, the baseAddress element may be used to indicate the offset. If not specified the offset is 0. The baseAddress is in units of the addressSpace addressUnitBits</xs:documentation></xs:annotation><xs:element name="baseAddress" type="ipxact:signedLongintExpression" minOccurs="0"><xs:annotation><xs:documentation>Base of an address space.</xs:documentation></xs:annotation></xs:element></xs:sequence></xs:extension></xs:complexContent></xs:complexType></xs:element></xs:sequence></xs:complexType></xs:element><xs:element name="slave"><xs:annotation><xs:documentation>If this element is present, the bus interface can serve as a slave.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:choice minOccurs="0"><xs:element ref="ipxact:memoryMapRef"/><xs:element ref="ipxact:transparentBridge" maxOccurs="unbounded"/></xs:choice><xs:element name="fileSetRefGroup" minOccurs="0" maxOccurs="unbounded"><xs:annotation><xs:documentation>This reference is used to point the filesets that are associated with this slave port.Depending on the slave port function, there may be completely different software drivers associated with the different ports. </xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="group" type="xs:Name" minOccurs="0"><xs:annotation><xs:documentation>Abritray name assigned to the collections of fileSets.</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:fileSetRef" minOccurs="0" maxOccurs="unbounded"/></xs:sequence><xs:attributeGroup ref="ipxact:id.att"/></xs:complexType></xs:element></xs:sequence></xs:complexType></xs:element><xs:element name="system"><xs:annotation><xs:documentation>If this element is present, the bus interface is a system interface, neither master nor slave, with a specific function on the bus.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:group"/></xs:sequence></xs:complexType></xs:element><xs:element name="mirroredSlave"><xs:annotation><xs:documentation>If this element is present, the bus interface represents a mirrored slave interface. All directional constraints on ports are reversed relative to the specification in the bus definition.</xs:documentation></xs:annotation><xs:complexType><xs:sequence minOccurs="0"><xs:element name="baseAddresses" minOccurs="0"><xs:annotation><xs:documentation>Represents a set of remap base addresses.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="remapAddress" maxOccurs="unbounded"><xs:annotation><xs:documentation>Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The state attribute indicates the name of the remap state for which this address is valid.</xs:documentation></xs:annotation><xs:complexType><xs:simpleContent><xs:extension base="ipxact:unsignedLongintExpression"><xs:attribute name="state" type="xs:string"><xs:annotation><xs:documentation>Name of the state in which this remapped address range is valid</xs:documentation></xs:annotation></xs:attribute><xs:attributeGroup ref="ipxact:id.att"/></xs:extension></xs:simpleContent></xs:complexType></xs:element><xs:element name="range" type="ipxact:unsignedPositiveLongintExpression"><xs:annotation><xs:documentation>The address range of mirrored slave, expressed as the number of bitsInLAU from the containing busInterface. </xs:documentation></xs:annotation></xs:element></xs:sequence></xs:complexType></xs:element></xs:sequence></xs:complexType></xs:element><xs:element name="mirroredMaster"><xs:annotation><xs:documentation>If this element is present, the bus interface represents a mirrored master interface. All directional constraints on ports are reversed relative to the specification in the bus definition.</xs:documentation></xs:annotation><xs:complexType/></xs:element><xs:element name="mirroredSystem"><xs:annotation><xs:documentation>If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:group"/></xs:sequence></xs:complexType></xs:element><xs:element name="monitor"><xs:annotation><xs:documentation>Indicates that this is a (passive) monitor interface. All of the ports in the interface must be inputs. The type of interface to be monitored is specified with the required interfaceType attribute. The ipxact:group element must be specified if monitoring a system interface.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:group" minOccurs="0"><xs:annotation><xs:documentation>Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition.</xs:documentation></xs:annotation></xs:element></xs:sequence><xs:attribute name="interfaceMode" use="required"><xs:simpleType><xs:restriction base="xs:token"><xs:enumeration value="master"/><xs:enumeration value="slave"/><xs:enumeration value="system"/><xs:enumeration value="mirroredMaster"/><xs:enumeration value="mirroredSlave"/><xs:enumeration value="mirroredSystem"/></xs:restriction></xs:simpleType></xs:attribute></xs:complexType></xs:element></xs:choice></xs:group><xs:element name="transparentBridge"><xs:annotation><xs:documentation>If this element is present, it indicates that the bus interface provides a transparent bridge to another master bus interface on the same component. It has a masterRef attribute which contains the name of the other bus interface.Any slave interface can bridge to multiple master interfaces, and multiple slave interfaces can bridge to the same master interface.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:isPresent" minOccurs="0"/></xs:sequence><xs:attribute name="masterRef" type="xs:Name" use="required"><xs:annotation><xs:documentation>The name of the master bus interface to which this interface bridges.</xs:documentation></xs:annotation></xs:attribute><xs:attributeGroup ref="ipxact:id.att"/></xs:complexType></xs:element><xs:group name="abstractorInterfaceMode"><xs:annotation><xs:documentation>Group of the different modes a busInterface can take on in an abstractor</xs:documentation></xs:annotation><xs:choice><xs:element name="master"><xs:annotation><xs:documentation>If this element is present, the bus interface can serve as a master. This element encapsulates additional information related to its role as master.</xs:documentation></xs:annotation></xs:element><xs:element name="slave"><xs:annotation><xs:documentation>If this element is present, the bus interface can serve as a slave.</xs:documentation></xs:annotation></xs:element><xs:element name="system"><xs:annotation><xs:documentation>If this element is present, the bus interface is a system interface, neither master nor slave, with a specific function on the bus.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:group"/></xs:sequence></xs:complexType></xs:element><xs:element name="mirroredSlave"><xs:annotation><xs:documentation>If this element is present, the bus interface represents a mirrored slave interface. All directional constraints on ports are reversed relative to the specification in the bus definition.</xs:documentation></xs:annotation></xs:element><xs:element name="mirroredMaster"><xs:annotation><xs:documentation>If this element is present, the bus interface represents a mirrored master interface. All directional constraints on ports are reversed relative to the specification in the bus definition.</xs:documentation></xs:annotation></xs:element><xs:element name="mirroredSystem"><xs:annotation><xs:documentation>If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:group"/></xs:sequence></xs:complexType></xs:element></xs:choice></xs:group><xs:complexType name="abstractorBusInterfaceType"><xs:annotation><xs:documentation>Type definition for a busInterface in a component</xs:documentation></xs:annotation><xs:sequence><xs:group ref="ipxact:nameGroup"/><xs:element ref="ipxact:abstractionTypes" minOccurs="0"/><xs:element ref="ipxact:parameters" minOccurs="0"/><xs:element ref="ipxact:vendorExtensions" minOccurs="0"/></xs:sequence><xs:attributeGroup ref="ipxact:any.att"/></xs:complexType><xs:element name="indirectInterface" type="ipxact:indirectInterfaceType"><xs:annotation><xs:documentation>Describes one of the bus interfaces supported by this component.</xs:documentation></xs:annotation></xs:element><xs:element name="indirectInterfaces"><xs:annotation><xs:documentation>A list of bus interfaces supported by this component.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:indirectInterface" maxOccurs="unbounded"/></xs:sequence></xs:complexType></xs:element><xs:complexType name="indirectInterfaceType"><xs:annotation><xs:documentation>Type definition for a indirectInterface in a component</xs:documentation></xs:annotation><xs:sequence><xs:group ref="ipxact:nameGroup"/><xs:element ref="ipxact:indirectAddressRef"/><xs:element ref="ipxact:indirectDataRef"/><xs:choice><xs:element name="memoryMapRef" type="xs:Name"><xs:annotation><xs:documentation>A reference to a memoryMap. This memoryMap is indirectly accessible through this interface.</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:transparentBridge" maxOccurs="unbounded"/></xs:choice><xs:element ref="ipxact:bitsInLau" minOccurs="0"/><xs:element name="endianness" type="ipxact:endianessType" minOccurs="0"><xs:annotation><xs:documentation>'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian.</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:parameters" minOccurs="0"/><xs:element ref="ipxact:vendorExtensions" minOccurs="0"/></xs:sequence><xs:anyAttribute namespace="##any" processContents="lax"/></xs:complexType><xs:element name="indirectAddressRef" type="xs:Name"><xs:annotation><xs:documentation>A reference to a field used for addressing the indirectly accessible memoryMap.</xs:documentation></xs:annotation></xs:element><xs:element name="indirectDataRef" type="xs:Name"><xs:annotation><xs:documentation>A reference to a field used for read/write access to the indirectly accessible memoryMap.</xs:documentation></xs:annotation></xs:element><xs:element name="abstractionTypes"><xs:complexType><xs:sequence><xs:element name="abstractionType" maxOccurs="unbounded"><xs:annotation><xs:documentation>The abstraction type/level of this interface. Refers to abstraction definition using vendor, library, name, version attributes along with any configurable element values needed to configure this abstraction. Bus definition can be found through a reference in this file.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:viewRef" minOccurs="0" maxOccurs="unbounded"><xs:annotation><xs:documentation>A reference to a view name in the file for which this type applies.</xs:documentation></xs:annotation></xs:element><xs:element name="abstractionRef" type="ipxact:configurableLibraryRefType"><xs:annotation><xs:documentation>Provides the VLNV of the abstraction type.</xs:documentation></xs:annotation></xs:element><xs:element name="portMaps" minOccurs="0"><xs:annotation><xs:documentation>Listing of maps between component ports and bus ports.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="portMap" maxOccurs="unbounded"><xs:annotation><xs:documentation>Maps a component's port to a port in a bus description. This is the logical to physical mapping. The logical pin comes from the bus interface and the physical pin from the component.</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element ref="ipxact:isPresent" minOccurs="0"/><xs:element name="logicalPort"><xs:annotation><xs:documentation>Logical port from abstraction definition</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="name" type="xs:Name"><xs:annotation><xs:documentation>Bus port name as specified inside the abstraction definition</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:range" minOccurs="0"/></xs:sequence></xs:complexType></xs:element><xs:choice><xs:element name="physicalPort"><xs:annotation><xs:documentation>Physical port from this component</xs:documentation></xs:annotation><xs:complexType><xs:sequence><xs:element name="name" type="ipxact:portName"><xs:annotation><xs:documentation>Component port name as specified inside the model port section</xs:documentation></xs:annotation></xs:element><xs:element ref="ipxact:partSelect" minOccurs="0"/></xs:sequence></xs:complexType></xs:element><xs:element name="logicalTieOff" type="ipxact:unsignedPositiveIntExpression"><xs:annotation><xs:documentation>Identifies a value to tie this logical port to.</xs:documentation></xs:annotation></xs:element></xs:choice><xs:element name="isInformative" type="xs:boolean" default="false" minOccurs="0"><xs:annotation><xs:documentation>When true, indicates that this portMap element is for information purpose only.</xs:documentation></xs:annotation></xs:element></xs:sequence><xs:attributeGroup ref="ipxact:id.att"/><xs:attribute name="invert" use="optional" default="false"><xs:annotation><xs:documentation>Indicates that the connection between the logical and physical ports should include an inversion.</xs:documentation></xs:annotation></xs:attribute></xs:complexType></xs:element></xs:sequence></xs:complexType></xs:element></xs:sequence><xs:attributeGroup ref="ipxact:id.att"/></xs:complexType></xs:element></xs:sequence></xs:complexType><xs:unique name="abstractionTypeViewRefUnique"><xs:selector xpath="ipxact:abstractionType/ipxact:viewRef"/><xs:field xpath="."/></xs:unique></xs:element></xs:schema>