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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> <HEAD> <META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8"> <TITLE>socgen_prj_description</TITLE> <META NAME="GENERATOR" CONTENT="OpenOffice.org 3.0 (Linux)"> <META NAME="CREATED" CONTENT="0;0"> <META NAME="CHANGED" CONTENT="20100309;9110600"> <META NAME="CLASSIFICATION" CONTENT="socgen project description"> <META NAME="DESCRIPTION" CONTENT="socgen is a laboratory for the development of a opensource design for reuse toolset"> <META NAME="KEYWORDS" CONTENT="eda design for reuse opensource tools"> <META NAME="Info 3" CONTENT=""> <META NAME="Info 4" CONTENT=""> <META NAME="date" CONTENT="2010-01-08T12:01:41-0500"> <META NAME="robots" CONTENT="index,follow"> </HEAD> <BODY LANG="en-US" DIR="LTR"> <DIV ID="toc__header" DIR="LTR"> <P><BR><BR> </P> </DIV> <H1><A NAME="socgen_project"></A>SOCGEN Project</H1> <H2>Design for Reuse</H2> <P>The SOCGEN project is a laboratory for developing and demonstrating the methods and processes needed to create and reuse digital components. The goal of the project is to create a open source set of eda tools that will enable a designer to configure and assemble a complete System_on_a_chip (SOC) in a quick, easy and error free manner.</P> <P>I am hosting this project on Opencores due to the availability of free opensourced ip modules and a user community that is in dire need of a good design for reuse solution. I will be taking various opencores modules and reworking them into the socgen repository. Design for reuse is all about efficiency. Any code can be reused if you devote enough time and energy to it but paying attention to the details can make a huge difference in how easy it is to reuse a module. Any one is welcome to use these versions of the modules and the scripts that I am creating. Feedback is always welcome.</P> <P>The entire industry is about to experience a change in the way that chips are designed that will be as dramatic as it was back in the early 90's. Before that point the most common tool for design entry was schematic capture. But designs had grown to the point where that was far to inefficient and it was replaced with a rtl to synthesis process.</P> <P>That happened 20 years ago and chips have continued to grow to the point where you can no longer design and verify the rtl code in a reasonable time. </P> <P>My approach to this problem is to introduce modern hi volume production line theory into the IC design process. The designs are too complex to simply get a group together and hand craft rtl code. Socgen will develop the tools and processes needed to assemble cores together in quick and predictable manner.</P> <P> </P> <P>A good deal of this effort involves understanding database design and usage. Most designers simply construct their databases based only on their immediate and past needs. Socgen will provide a repository of various projects that have been converted to show how small changes in where you store files can make a big difference in how easily those files can be reused.</P> <P><BR><BR> </P> <P>All socgen tools and components are released under LGPL. Any other opencores projects used in the repository will retain their original license.</P> <P><BR><BR> </P> <P><BR><BR> </P> <P><BR><BR> </P> <P><BR><BR> </P> <P><BR><BR> </P> <P><BR><BR> </P> <P>Socgen will provide:</P> <OL> <LI><P>Installation instructions for any and all external tools needed</P> <LI><P>Proper data base design and management tools and techniques</P> <LI><P>Proper design verification</P> <LI><P>All modules will be proven in silicon</P> </OL> <P><BR><BR> </P> <P>Socgen is a work in process so expect to see frequent changes. All socgen tools are run under Makefiles and I will try to keep the top level commands constant.</P> <P><BR><BR> </P> <P>Till Later</P> <P><BR><BR> </P> <P>John Eaton</P> <P><BR><BR> </P> <P><BR><BR> </P> </BODY> </HTML>