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Design Assistant report for sport_topFri Feb 20 13:59:38 2015Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Design Assistant Summary3. Design Assistant Settings4. High Violations5. Medium Violations6. Information only Violations7. Design Assistant Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2014 Altera Corporation. All rights reserved.Your use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, the Altera Quartus II License Agreement,the Altera MegaCore Function License Agreement, or otherapplicable license agreement, including, without limitation,that your use is for the sole purpose of programming logicdevices manufactured by Altera and sold by Altera or itsauthorized distributors. Please refer to the applicableagreement for further details.+-------------------------------------------------------------------------+; Design Assistant Summary ;+-----------------------------------+-------------------------------------+; Design Assistant Status ; Analyzed - Fri Feb 20 13:59:38 2015 ;; Revision Name ; sport_top ;; Top-level Entity Name ; sport_top ;; Family ; Cyclone IV GX ;; Total Critical Violations ; 0 ;; Total High Violations ; 31 ;; - Rule D101 ; 16 ;; - Rule D103 ; 15 ;; Total Medium Violations ; 2 ;; - Rule R102 ; 1 ;; - Rule D102 ; 1 ;; Total Information only Violations ; 51 ;; - Rule T101 ; 1 ;; - Rule T102 ; 50 ;+-----------------------------------+-------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Design Assistant Settings ;+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----+; Option ; Setting ; To ;+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----+; Design Assistant mode ; Post-Synthesis ; ;; Threshold value for clock net not mapped to clock spines rule ; 25 ; ;; Minimum number of clock port feed by gated clocks ; 30 ; ;; Minimum number of node fan-out ; 30 ; ;; Maximum number of nodes to report ; 50 ; ;; Rule C101: Gated clock should be implemented according to the Altera standard scheme ; On ; ;; Rule C102: Logic cell should not be used to generate an inverted clock signal ; On ; ;; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; On ; ;; Rule C104: Clock signal source should drive only clock input ports ; On ; ;; Rule C105: Clock signal should be a global signal (You set a Design Assistant configuration rule to check for clocks with a certain number of fanouts. You specified a reporting threshold of <number> fanouts. The following clocks all contain more than <number> fanouts. You can either adjust the reporting threshold in the Design Assistant Settings page, or change the following clock signals to global signals.) ; On ; ;; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; On ; ;; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ;; Rule R102: External reset signals should be synchronized using two cascaded registers ; On ; ;; Rule R103: External reset signal should be correctly synchronized ; On ; ;; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized ; On ; ;; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized ; On ; ;; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ;; Rule T102: Top nodes with the highest number of fan-outs ; On ; ;; Rule A101: Design should not contain combinational loops ; On ; ;; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ;; Rule A103: Design should not contain delay chains ; On ; ;; Rule A104: Design should not contain ripple clock structures ; On ; ;; Rule A105: Pulses should not be implemented asynchronously ; On ; ;; Rule A106: Multiple pulses should not be generated in design ; On ; ;; Rule A107: Design should not contain SR latches ; On ; ;; Rule A108: Design should not contain latches ; On ; ;; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ;; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ;; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source ; On ; ;; Rule S104: Clock port and any other port of a register should not be driven by the same signal source ; On ; ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ;; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ;; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains ; Off ; ;; Rule M102: No reset signal defined to initialize the state machine ; Off ; ;; Rule M103: State machine should not contain an unreachable state ; Off ; ;; Rule M104: State machine should not contain a deadlock state ; Off ; ;; Rule M105: State machine should not contain a dead transition ; Off ; ;+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+----++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; High Violations ;+------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+; Rule name ; Name ;+------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 1 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[7] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 2 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[6] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 3 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[4] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 4 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[5] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 5 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[2] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 6 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[3] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 7 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[1] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 8 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[0] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 9 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[9] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 10 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[8] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 11 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[13] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.001 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 12 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[12] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.001 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 13 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[11] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.001 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 14 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[10] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.001 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 15 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[14] ;; Destination node(s) from clock "txclk" ; state.010 ;; Destination node(s) from clock "txclk" ; state.001 ;; Destination node(s) from clock "txclk" ; state.011 ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 16 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[16] ;; Destination node(s) from clock "txclk" ; tx_start_tx ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 1 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[7] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 2 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[6] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 3 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[4] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 4 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[5] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 5 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[2] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 6 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[3] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 7 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[1] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 8 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[0] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 9 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[9] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 10 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[8] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 11 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[13] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 12 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[12] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 13 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[11] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 14 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[10] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 15 ; ;; Source node(s) from clock "wb_clk_i" ; wb_interface_sport:wb_interface|txreg[14] ;; Synchronizer node(s) from clock "txclk" ; state.011 ;; Synchronizer node(s) from clock "txclk" ; txFS ;+------------------------------------------------------------------------------------------------------------------------+-------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Medium Violations ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+; Rule name ; Name ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+; Rule R102: External reset signals should be synchronized using two cascaded registers ; wb_rst_i ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[7] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[20] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[6] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[4] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[5] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[2] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[3] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[1] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[0] ;; Reset signal destination node(s) list ; wb_interface_sport:wb_interface|txreg[9] ;; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 1 ; ;; Source node(s) from clock "wb_clk_i" - (Bus) ; wb_interface_sport:wb_interface|txreg ;; Synchronizer node(s) from clock "txclk" ; state.011 ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------++--------------------------------------------------------------------------------------------------------------------------+; Information only Violations ;+------------------------------------------------------------------+---------------------------------------------+---------+; Rule name ; Name ; Fan-Out ;+------------------------------------------------------------------+---------------------------------------------+---------+; Rule T101: Nodes with more than the specified number of fan-outs ; wb_interface_sport:wb_interface|wb_dat_o~31 ; 32 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|wb_dat_o~31 ; 32 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|always4~1 ; 18 ;; Rule T102: Top nodes with the highest number of fan-outs ; state.010 ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; txsampleCnt_tx[1] ; 4 ;; Rule T102: Top nodes with the highest number of fan-outs ; txsampleCnt_tx[0] ; 4 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[4] ; 3 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|Equal1~0 ; 3 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[2] ; 3 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|always3~1 ; 3 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[3] ; 3 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[7] ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[8] ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; Equal0~1 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; Equal1~5 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[5] ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; Selector1~0 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[6] ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; state.011 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; Equal1~0 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; Equal0~2 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; tx_start_tx ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; Equal0~0 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; state.001 ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|txreg[0] ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[9] ; 2 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_dat_i[10] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|txreg[3] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; Selector1~1 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_rst_i ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_dat_i[13] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; Equal1~4 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_dat_i[6] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_clk_i ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[6]~18 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[5]~17 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_dat_i[12] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[4]~15 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_dat_i[3] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[3]~13 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_adr_i[5] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[2]~11 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; Equal1~3 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[2]~9 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|always4~0 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_interface_sport:wb_interface|txreg[4] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txsampleCnt_tx[1]~4 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_dat_i[9] ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txsampleCnt_tx[0]~3 ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; wb_stb_i ; 1 ;; Rule T102: Top nodes with the highest number of fan-outs ; txpacketCnt_tx[8]~22 ; 1 ;+------------------------------------------------------------------+---------------------------------------------+---------++---------------------------+; Design Assistant Messages ;+---------------------------+Info: *******************************************************************Info: Running Quartus II 64-Bit Design AssistantInfo: Version 14.0.0 Build 200 06/17/2014 SJ Web EditionInfo: Processing started: Fri Feb 20 13:59:37 2015Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off sport_top -c sport_topInfo (119006): Selected device EP4CGX15BF14C6 for design "sport_top"Critical Warning (332012): Synopsys Design Constraints File file not found: 'sport_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.Info (332144): No user constrained base clocks found in the designInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 16 asynchronous clock domain interface structure(s) related to this rule.Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[7]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[6]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[4]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[5]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[2]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[3]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[1]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[0]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[9]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[8]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[13]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[12]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[11]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[10]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[14]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[16]"Critical Warning (308067): (High) Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 15 asynchronous clock domain interface structure(s) related to this rule.Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[7]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[6]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[4]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[5]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[2]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[3]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[1]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[0]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[9]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[8]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[13]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[12]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[11]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[10]"Critical Warning (308012): Node "wb_interface_sport:wb_interface|txreg[14]"Warning (308023): (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule.Warning (308010): Node "wb_rst_i"Warning (308071): (Medium) Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain. (Value defined:2). Found 1 asynchronous clock domain interface structure(s) related to this rule.Warning (308010): Node "wb_interface_sport:wb_interface|txreg (Bus)"Info (308046): (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 1 node(s) with highest fan-out.Info (308011): Node "wb_interface_sport:wb_interface|wb_dat_o~31"Info (308044): (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.Info (308011): Node "wb_interface_sport:wb_interface|wb_dat_o~31"Info (308011): Node "wb_interface_sport:wb_interface|always4~1"Info (308011): Node "state.010"Info (308011): Node "txsampleCnt_tx[1]"Info (308011): Node "txsampleCnt_tx[0]"Info (308011): Node "txpacketCnt_tx[4]"Info (308011): Node "wb_interface_sport:wb_interface|Equal1~0"Info (308011): Node "txpacketCnt_tx[2]"Info (308011): Node "wb_interface_sport:wb_interface|always3~1"Info (308011): Node "txpacketCnt_tx[3]"Info (308011): Node "txpacketCnt_tx[7]"Info (308011): Node "txpacketCnt_tx[8]"Info (308011): Node "Equal0~1"Info (308011): Node "Equal1~5"Info (308011): Node "txpacketCnt_tx[5]"Info (308011): Node "Selector1~0"Info (308011): Node "txpacketCnt_tx[6]"Info (308011): Node "state.011"Info (308011): Node "Equal1~0"Info (308011): Node "Equal0~2"Info (308011): Node "tx_start_tx"Info (308011): Node "Equal0~0"Info (308011): Node "state.001"Info (308011): Node "wb_interface_sport:wb_interface|txreg[0]"Info (308011): Node "txpacketCnt_tx[9]"Info (308011): Node "wb_dat_i[10]"Info (308011): Node "wb_interface_sport:wb_interface|txreg[3]"Info (308011): Node "Selector1~1"Info (308011): Node "wb_rst_i"Info (308011): Node "wb_dat_i[13]"Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.Info (308006): Design Assistant information: finished post-synthesis analysis of current design -- generated 51 information messages and 33 warning messagesInfo: Quartus II 64-Bit Design Assistant was successful. 0 errors, 38 warningsInfo: Peak virtual memory: 474 megabytesInfo: Processing ended: Fri Feb 20 13:59:38 2015Info: Elapsed time: 00:00:01Info: Total CPU time (on all processors): 00:00:01