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Flow report for sport_top
Fri Feb 20 13:59:44 2015
Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log
  8. Flow Messages
  9. Flow Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+---------------------------------------------------------------------------------+
; Flow Summary                                                                    ;
+------------------------------------+--------------------------------------------+
; Flow Status                        ; Flow Failed - Fri Feb 20 13:59:44 2015     ;
; Quartus II 64-Bit Version          ; 14.0.0 Build 200 06/17/2014 SJ Web Edition ;
; Revision Name                      ; sport_top                                  ;
; Top-level Entity Name              ; sport_top                                  ;
; Family                             ; Cyclone IV GX                              ;
; Device                             ; EP4CGX15BF14C6                             ;
; Timing Models                      ; Final                                      ;
; Total logic elements               ; 61                                         ;
;     Total combinational functions  ; 38 / 14,400 ( < 1 % )                      ;
;     Dedicated logic registers      ; 39 / 14,400 ( < 1 % )                      ;
; Total registers                    ; 39                                         ;
; Total pins                         ; 89 / 81 ( 110 % )                          ;
; Total virtual pins                 ; 0                                          ;
; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
; Embedded Multiplier 9-bit elements ; 0                                          ;
; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
+------------------------------------+--------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 02/20/2015 13:59:33 ;
; Main task         ; Compilation         ;
; Revision Name     ; sport_top           ;
+-------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                    ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; Assignment Name                     ; Value                          ; Default Value ; Entity Name ; Section Id     ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID               ; 61959091049986.142445877304824 ; --            ; --          ; --             ;
; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                    ; --            ; --          ; eda_simulation ;
; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)      ; <None>        ; --          ; --             ;
; MAX_CORE_JUNCTION_TEMP              ; 85                             ; --            ; --          ; --             ;
; MIN_CORE_JUNCTION_TEMP              ; 0                              ; --            ; --          ; --             ;
; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                           ; --            ; --          ; --             ;
; PARTITION_COLOR                     ; 16764057                       ; --            ; --          ; Top            ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING          ; --            ; --          ; Top            ;
; PARTITION_NETLIST_TYPE              ; SOURCE                         ; --            ; --          ; Top            ;
; PROJECT_OUTPUT_DIRECTORY            ; output_files                   ; --            ; --          ; --             ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ; 571 MB              ; 00:00:02                           ;
; Design Assistant        ; 00:00:01     ; 1.0                     ; 474 MB              ; 00:00:01                           ;
; I/O Assignment Analysis ; 00:00:02     ; 1.0                     ; 663 MB              ; 00:00:02                           ;
; Total                   ; 00:00:05     ; --                      ; --                  ; 00:00:05                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


+--------------------------------------------------------------------------------------+
; Flow OS Summary                                                                      ;
+-------------------------+------------------+-----------+------------+----------------+
; Module Name             ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
+-------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis    ; jeffA-PC         ; Windows 7 ; 6.1        ; x86_64         ;
; Design Assistant        ; jeffA-PC         ; Windows 7 ; 6.1        ; x86_64         ;
; I/O Assignment Analysis ; jeffA-PC         ; Windows 7 ; 6.1        ; x86_64         ;
+-------------------------+------------------+-----------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off sport_top -c sport_top
quartus_drc --read_settings_files=off --write_settings_files=off sport_top -c sport_top
quartus_fit --read_settings_files=on --write_settings_files=off sport_top -c sport_top --floorplan