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<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">wb_dat_i&lt;31&gt;</arg> has no load.
</msg>

<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">14</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">wb_dat_i&lt;30&gt;,
wb_dat_i&lt;29&gt;,
wb_dat_i&lt;28&gt;,
wb_dat_i&lt;27&gt;,
wb_dat_i&lt;26&gt;</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
</msg>

<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">DRxSEC_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">DRxPRI_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

</messages>