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[/] [sport/] [trunk/] [syn/] [xilinx/] [ise/] [sport_top/] [sport_top.twr] - Rev 7
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--------------------------------------------------------------------------------Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4-n 3 -fastpaths -xml sport_top.twx sport_top.ncd -o sport_top.twr sport_top.pcf-ucf sport_top.ucfDesign file: sport_top.ncdPhysical constraint file: sport_top.pcfDevice,package,speed: xc3s700an,fgg484,-4 (PRODUCTION 1.42 2013-10-13)Report level: verbose reportEnvironment Variable Effect-------------------- ------NONE No environment variables were set--------------------------------------------------------------------------------INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained pathsoption. All paths that are not constrained will be reported in theunconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based ona 50 Ohm transmission line loading model. For the details of this model,and for more information on accounting for different loading conditions,please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jittervalue, please add SYSTEM_JITTER constraint to the UCF to modify the ClockUncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and'Phase Error' calculations, these terms will be zero in the ClockUncertainty calculation. Please make appropriate modification toSYSTEM_JITTER to account for the unsupported Discrete Jitter and PhaseError.================================================================================Timing constraint: TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns HIGH 50%;For more information, see Period Analysis in the Timing Closure User Guide (UG612).0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints0 timing errors detected. (0 component switching limit errors)Minimum period is 1.602ns.--------------------------------------------------------------------------------Component Switching Limit Checks: TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns HIGH 50%;--------------------------------------------------------------------------------Slack: 18.398ns (period - (min low pulse limit / (low pulse / period)))Period: 20.000nsLow pulse: 10.000nsLow pulse limit: 0.801ns (Tcl)Physical resource: rxfs_rnm0/CLKLogical resource: rxfs_rnm0/CKLocation pin: SLICE_X6Y54.CLKClock network: RSCLKx_OBUF--------------------------------------------------------------------------------Slack: 18.398ns (period - (min high pulse limit / (high pulse / period)))Period: 20.000nsHigh pulse: 10.000nsHigh pulse limit: 0.801ns (Tch)Physical resource: rxfs_rnm0/CLKLogical resource: rxfs_rnm0/CKLocation pin: SLICE_X6Y54.CLKClock network: RSCLKx_OBUF--------------------------------------------------------------------------------Slack: 18.398ns (period - min period limit)Period: 20.000nsMin period limit: 1.602ns (624.220MHz) (Tcp)Physical resource: rxfs_rnm0/CLKLogical resource: rxfs_rnm0/CKLocation pin: SLICE_X6Y54.CLKClock network: RSCLKx_OBUF--------------------------------------------------------------------------------================================================================================Timing constraint: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;For more information, see Period Analysis in the Timing Closure User Guide (UG612).128 paths analyzed, 60 endpoints analyzed, 0 failing endpoints0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)Minimum period is 4.635ns.--------------------------------------------------------------------------------Paths for end point state_FSM_FFd2 (SLICE_X4Y53.F2), 10 paths--------------------------------------------------------------------------------Slack (setup path): 15.365ns (requirement - (data path - clock path skew + uncertainty))Source: txpacketCnt_tx_7 (FF)Destination: state_FSM_FFd2 (FF)Requirement: 20.000nsData Path Delay: 4.672ns (Levels of Logic = 3)Clock Path Skew: 0.037ns (0.056 - 0.019)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txpacketCnt_tx_7 to state_FSM_FFd2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y60.XQ Tcko 0.631 txpacketCnt_tx<7>txpacketCnt_tx_7SLICE_X5Y51.G3 net (fanout=2) 1.234 txpacketCnt_tx<7>SLICE_X5Y51.COUT Topcyg 1.178 Mcompar_state_cmp_eq0001_cy<3>Mcompar_state_cmp_eq0001_lut<3>Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.XB Tcinxb 0.296 Mcompar_state_cmp_eq0001_cy<4>Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.F2 net (fanout=1) 0.531 Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd2------------------------------------------------- ---------------------------Total 4.672ns (2.907ns logic, 1.765ns route)(62.2% logic, 37.8% route)--------------------------------------------------------------------------------Slack (setup path): 15.387ns (requirement - (data path - clock path skew + uncertainty))Source: txpacketCnt_tx_3 (FF)Destination: state_FSM_FFd2 (FF)Requirement: 20.000nsData Path Delay: 4.634ns (Levels of Logic = 4)Clock Path Skew: 0.021ns (0.056 - 0.035)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txpacketCnt_tx_3 to state_FSM_FFd2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y58.XQ Tcko 0.631 txpacketCnt_tx<3>txpacketCnt_tx_3SLICE_X5Y50.G2 net (fanout=2) 1.066 txpacketCnt_tx<3>SLICE_X5Y50.COUT Topcyg 1.178 Mcompar_state_cmp_eq0001_cy<1>Mcompar_state_cmp_eq0001_lut<1>Mcompar_state_cmp_eq0001_cy<1>SLICE_X5Y51.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<1>SLICE_X5Y51.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<3>Mcompar_state_cmp_eq0001_cy<2>Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.XB Tcinxb 0.296 Mcompar_state_cmp_eq0001_cy<4>Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.F2 net (fanout=1) 0.531 Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd2------------------------------------------------- ---------------------------Total 4.634ns (3.037ns logic, 1.597ns route)(65.5% logic, 34.5% route)--------------------------------------------------------------------------------Slack (setup path): 15.400ns (requirement - (data path - clock path skew + uncertainty))Source: txpacketCnt_tx_4 (FF)Destination: state_FSM_FFd2 (FF)Requirement: 20.000nsData Path Delay: 4.637ns (Levels of Logic = 3)Clock Path Skew: 0.037ns (0.056 - 0.019)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txpacketCnt_tx_4 to state_FSM_FFd2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y61.YQ Tcko 0.676 txpacketCnt_tx<5>txpacketCnt_tx_4SLICE_X5Y51.F3 net (fanout=2) 1.137 txpacketCnt_tx<4>SLICE_X5Y51.COUT Topcyf 1.195 Mcompar_state_cmp_eq0001_cy<3>Mcompar_state_cmp_eq0001_lut<2>Mcompar_state_cmp_eq0001_cy<2>Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.XB Tcinxb 0.296 Mcompar_state_cmp_eq0001_cy<4>Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.F2 net (fanout=1) 0.531 Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd2------------------------------------------------- ---------------------------Total 4.637ns (2.969ns logic, 1.668ns route)(64.0% logic, 36.0% route)--------------------------------------------------------------------------------Paths for end point state_FSM_FFd2 (SLICE_X4Y53.F3), 5 paths--------------------------------------------------------------------------------Slack (setup path): 15.427ns (requirement - (data path - clock path skew + uncertainty))Source: txsampleCnt_tx_4 (FF)Destination: state_FSM_FFd2 (FF)Requirement: 20.000nsData Path Delay: 4.569ns (Levels of Logic = 4)Clock Path Skew: -0.004ns (0.056 - 0.060)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txsampleCnt_tx_4 to state_FSM_FFd2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y55.XQ Tcko 0.631 txsampleCnt_tx<4>txsampleCnt_tx_4SLICE_X5Y53.G2 net (fanout=2) 0.903 txsampleCnt_tx<4>SLICE_X5Y53.Y Tilo 0.648 state_FSM_FFd1-In_bdd2state_FSM_FFd1-In51SLICE_X5Y53.F4 net (fanout=1) 0.044 state_FSM_FFd1-In51/OSLICE_X5Y53.X Tilo 0.643 state_FSM_FFd1-In_bdd2state_FSM_FFd1-In31SLICE_X4Y53.G4 net (fanout=2) 0.148 state_FSM_FFd1-In_bdd2SLICE_X4Y53.Y Tilo 0.707 state_FSM_FFd2state_FSM_FFd1-In21_SW0SLICE_X4Y53.F3 net (fanout=1) 0.043 state_FSM_FFd1-In21_SW0/OSLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd2------------------------------------------------- ---------------------------Total 4.569ns (3.431ns logic, 1.138ns route)(75.1% logic, 24.9% route)--------------------------------------------------------------------------------Slack (setup path): 15.471ns (requirement - (data path - clock path skew + uncertainty))Source: txsampleCnt_tx_1 (FF)Destination: state_FSM_FFd2 (FF)Requirement: 20.000nsData Path Delay: 4.525ns (Levels of Logic = 4)Clock Path Skew: -0.004ns (0.056 - 0.060)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txsampleCnt_tx_1 to state_FSM_FFd2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X5Y54.XQ Tcko 0.591 txsampleCnt_tx<1>txsampleCnt_tx_1SLICE_X4Y54.F1 net (fanout=4) 0.579 txsampleCnt_tx<1>SLICE_X4Y54.X Tilo 0.692 txsampleCnt_tx<2>state_FSM_FFd1-In41_SW0SLICE_X5Y53.F3 net (fanout=1) 0.320 N21SLICE_X5Y53.X Tilo 0.643 state_FSM_FFd1-In_bdd2state_FSM_FFd1-In31SLICE_X4Y53.G4 net (fanout=2) 0.148 state_FSM_FFd1-In_bdd2SLICE_X4Y53.Y Tilo 0.707 state_FSM_FFd2state_FSM_FFd1-In21_SW0SLICE_X4Y53.F3 net (fanout=1) 0.043 state_FSM_FFd1-In21_SW0/OSLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd2------------------------------------------------- ---------------------------Total 4.525ns (3.435ns logic, 1.090ns route)(75.9% logic, 24.1% route)--------------------------------------------------------------------------------Slack (setup path): 15.651ns (requirement - (data path - clock path skew + uncertainty))Source: txsampleCnt_tx_3 (FF)Destination: state_FSM_FFd2 (FF)Requirement: 20.000nsData Path Delay: 4.345ns (Levels of Logic = 4)Clock Path Skew: -0.004ns (0.056 - 0.060)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txsampleCnt_tx_3 to state_FSM_FFd2Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X5Y55.XQ Tcko 0.591 txsampleCnt_tx<3>txsampleCnt_tx_3SLICE_X5Y53.G4 net (fanout=3) 0.719 txsampleCnt_tx<3>SLICE_X5Y53.Y Tilo 0.648 state_FSM_FFd1-In_bdd2state_FSM_FFd1-In51SLICE_X5Y53.F4 net (fanout=1) 0.044 state_FSM_FFd1-In51/OSLICE_X5Y53.X Tilo 0.643 state_FSM_FFd1-In_bdd2state_FSM_FFd1-In31SLICE_X4Y53.G4 net (fanout=2) 0.148 state_FSM_FFd1-In_bdd2SLICE_X4Y53.Y Tilo 0.707 state_FSM_FFd2state_FSM_FFd1-In21_SW0SLICE_X4Y53.F3 net (fanout=1) 0.043 state_FSM_FFd1-In21_SW0/OSLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd2------------------------------------------------- ---------------------------Total 4.345ns (3.391ns logic, 0.954ns route)(78.0% logic, 22.0% route)--------------------------------------------------------------------------------Paths for end point txpacketCnt_tx_9 (SLICE_X4Y62.F2), 10 paths--------------------------------------------------------------------------------Slack (setup path): 15.504ns (requirement - (data path - clock path skew + uncertainty))Source: txpacketCnt_tx_1 (FF)Destination: txpacketCnt_tx_9 (FF)Requirement: 20.000nsData Path Delay: 4.467ns (Levels of Logic = 6)Clock Path Skew: -0.029ns (0.006 - 0.035)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txpacketCnt_tx_1 to txpacketCnt_tx_9Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y59.XQ Tcko 0.631 txpacketCnt_tx<1>txpacketCnt_tx_1SLICE_X5Y58.G1 net (fanout=2) 0.528 txpacketCnt_tx<1>SLICE_X5Y58.COUT Topcyg 1.178 txpacketCnt_tx_addsub0000<0>txpacketCnt_tx<1>_rtMadd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<2>Madd_txpacketCnt_tx_addsub0000_cy<2>Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<4>Madd_txpacketCnt_tx_addsub0000_cy<4>Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<6>Madd_txpacketCnt_tx_addsub0000_cy<6>Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.Y Tciny 0.864 txpacketCnt_tx_addsub0000<8>Madd_txpacketCnt_tx_addsub0000_cy<8>Madd_txpacketCnt_tx_addsub0000_xor<9>SLICE_X4Y62.F2 net (fanout=1) 0.074 txpacketCnt_tx_addsub0000<9>SLICE_X4Y62.CLK Tfck 0.802 txpacketCnt_tx<9>txpacketCnt_tx_mux0000<9>1txpacketCnt_tx_9------------------------------------------------- ---------------------------Total 4.467ns (3.865ns logic, 0.602ns route)(86.5% logic, 13.5% route)--------------------------------------------------------------------------------Slack (setup path): 15.560ns (requirement - (data path - clock path skew + uncertainty))Source: txpacketCnt_tx_0 (FF)Destination: txpacketCnt_tx_9 (FF)Requirement: 20.000nsData Path Delay: 4.411ns (Levels of Logic = 6)Clock Path Skew: -0.029ns (0.006 - 0.035)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txpacketCnt_tx_0 to txpacketCnt_tx_9Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y59.YQ Tcko 0.676 txpacketCnt_tx<1>txpacketCnt_tx_0SLICE_X5Y58.F4 net (fanout=2) 0.410 txpacketCnt_tx<0>SLICE_X5Y58.COUT Topcyf 1.195 txpacketCnt_tx_addsub0000<0>Madd_txpacketCnt_tx_addsub0000_lut<0>_INV_0Madd_txpacketCnt_tx_addsub0000_cy<0>Madd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<2>Madd_txpacketCnt_tx_addsub0000_cy<2>Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<4>Madd_txpacketCnt_tx_addsub0000_cy<4>Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<6>Madd_txpacketCnt_tx_addsub0000_cy<6>Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.Y Tciny 0.864 txpacketCnt_tx_addsub0000<8>Madd_txpacketCnt_tx_addsub0000_cy<8>Madd_txpacketCnt_tx_addsub0000_xor<9>SLICE_X4Y62.F2 net (fanout=1) 0.074 txpacketCnt_tx_addsub0000<9>SLICE_X4Y62.CLK Tfck 0.802 txpacketCnt_tx<9>txpacketCnt_tx_mux0000<9>1txpacketCnt_tx_9------------------------------------------------- ---------------------------Total 4.411ns (3.927ns logic, 0.484ns route)(89.0% logic, 11.0% route)--------------------------------------------------------------------------------Slack (setup path): 15.564ns (requirement - (data path - clock path skew + uncertainty))Source: txpacketCnt_tx_2 (FF)Destination: txpacketCnt_tx_9 (FF)Requirement: 20.000nsData Path Delay: 4.407ns (Levels of Logic = 5)Clock Path Skew: -0.029ns (0.006 - 0.035)Source Clock: TSCLKx_OBUF rising at 0.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMaximum Data Path: txpacketCnt_tx_2 to txpacketCnt_tx_9Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y58.YQ Tcko 0.676 txpacketCnt_tx<3>txpacketCnt_tx_2SLICE_X5Y59.F3 net (fanout=2) 0.536 txpacketCnt_tx<2>SLICE_X5Y59.COUT Topcyf 1.195 txpacketCnt_tx_addsub0000<2>txpacketCnt_tx<2>_rtMadd_txpacketCnt_tx_addsub0000_cy<2>Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<4>Madd_txpacketCnt_tx_addsub0000_cy<4>Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<6>Madd_txpacketCnt_tx_addsub0000_cy<6>Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.Y Tciny 0.864 txpacketCnt_tx_addsub0000<8>Madd_txpacketCnt_tx_addsub0000_cy<8>Madd_txpacketCnt_tx_addsub0000_xor<9>SLICE_X4Y62.F2 net (fanout=1) 0.074 txpacketCnt_tx_addsub0000<9>SLICE_X4Y62.CLK Tfck 0.802 txpacketCnt_tx<9>txpacketCnt_tx_mux0000<9>1txpacketCnt_tx_9------------------------------------------------- ---------------------------Total 4.407ns (3.797ns logic, 0.610ns route)(86.2% logic, 13.8% route)--------------------------------------------------------------------------------Hold Paths: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;--------------------------------------------------------------------------------Paths for end point txsampleCnt_tx_1 (SLICE_X5Y54.F4), 1 path--------------------------------------------------------------------------------Slack (hold path): 1.314ns (requirement - (clock path skew + uncertainty - data path))Source: txsampleCnt_tx_1 (FF)Destination: txsampleCnt_tx_1 (FF)Requirement: 0.000nsData Path Delay: 1.314ns (Levels of Logic = 1)Clock Path Skew: 0.000nsSource Clock: TSCLKx_OBUF rising at 20.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMinimum Data Path: txsampleCnt_tx_1 to txsampleCnt_tx_1Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X5Y54.XQ Tcko 0.473 txsampleCnt_tx<1>txsampleCnt_tx_1SLICE_X5Y54.F4 net (fanout=4) 0.375 txsampleCnt_tx<1>SLICE_X5Y54.CLK Tckf (-Th) -0.466 txsampleCnt_tx<1>txsampleCnt_tx_mux0000<1>1txsampleCnt_tx_1------------------------------------------------- ---------------------------Total 1.314ns (0.939ns logic, 0.375ns route)(71.5% logic, 28.5% route)--------------------------------------------------------------------------------Paths for end point txsampleCnt_tx_0 (SLICE_X5Y54.G4), 1 path--------------------------------------------------------------------------------Slack (hold path): 1.363ns (requirement - (clock path skew + uncertainty - data path))Source: state_FSM_FFd2 (FF)Destination: txsampleCnt_tx_0 (FF)Requirement: 0.000nsData Path Delay: 1.367ns (Levels of Logic = 1)Clock Path Skew: 0.004ns (0.060 - 0.056)Source Clock: TSCLKx_OBUF rising at 20.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMinimum Data Path: state_FSM_FFd2 to txsampleCnt_tx_0Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y53.XQ Tcko 0.505 state_FSM_FFd2state_FSM_FFd2SLICE_X5Y54.G4 net (fanout=18) 0.392 state_FSM_FFd2SLICE_X5Y54.CLK Tckg (-Th) -0.470 txsampleCnt_tx<1>txsampleCnt_tx_mux0000<0>1txsampleCnt_tx_0------------------------------------------------- ---------------------------Total 1.367ns (0.975ns logic, 0.392ns route)(71.3% logic, 28.7% route)--------------------------------------------------------------------------------Paths for end point txsampleCnt_tx_3 (SLICE_X5Y55.F3), 1 path--------------------------------------------------------------------------------Slack (hold path): 1.418ns (requirement - (clock path skew + uncertainty - data path))Source: state_FSM_FFd2 (FF)Destination: txsampleCnt_tx_3 (FF)Requirement: 0.000nsData Path Delay: 1.422ns (Levels of Logic = 1)Clock Path Skew: 0.004ns (0.060 - 0.056)Source Clock: TSCLKx_OBUF rising at 20.000nsDestination Clock: TSCLKx_OBUF rising at 20.000nsClock Uncertainty: 0.000nsMinimum Data Path: state_FSM_FFd2 to txsampleCnt_tx_3Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X4Y53.XQ Tcko 0.505 state_FSM_FFd2state_FSM_FFd2SLICE_X5Y55.F3 net (fanout=18) 0.451 state_FSM_FFd2SLICE_X5Y55.CLK Tckf (-Th) -0.466 txsampleCnt_tx<3>txsampleCnt_tx_mux0000<3>1txsampleCnt_tx_3------------------------------------------------- ---------------------------Total 1.422ns (0.971ns logic, 0.451ns route)(68.3% logic, 31.7% route)--------------------------------------------------------------------------------Component Switching Limit Checks: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;--------------------------------------------------------------------------------Slack: 18.398ns (period - (min low pulse limit / (low pulse / period)))Period: 20.000nsLow pulse: 10.000nsLow pulse limit: 0.801ns (Tcl)Physical resource: state_FSM_FFd1/CLKLogical resource: state_FSM_FFd1/CKLocation pin: SLICE_X4Y52.CLKClock network: TSCLKx_OBUF--------------------------------------------------------------------------------Slack: 18.398ns (period - (min high pulse limit / (high pulse / period)))Period: 20.000nsHigh pulse: 10.000nsHigh pulse limit: 0.801ns (Tch)Physical resource: state_FSM_FFd1/CLKLogical resource: state_FSM_FFd1/CKLocation pin: SLICE_X4Y52.CLKClock network: TSCLKx_OBUF--------------------------------------------------------------------------------Slack: 18.398ns (period - min period limit)Period: 20.000nsMin period limit: 1.602ns (624.220MHz) (Tcp)Physical resource: state_FSM_FFd1/CLKLogical resource: state_FSM_FFd1/CKLocation pin: SLICE_X4Y52.CLKClock network: TSCLKx_OBUF--------------------------------------------------------------------------------================================================================================Timing constraint: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;For more information, see Period Analysis in the Timing Closure User Guide (UG612).22 paths analyzed, 22 endpoints analyzed, 0 failing endpoints0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)Minimum period is 3.204ns.--------------------------------------------------------------------------------Paths for end point wb_interface/rxreg_20 (SLICE_X1Y54.CE), 1 path--------------------------------------------------------------------------------Slack (setup path): 6.860ns (requirement - (data path - clock path skew + uncertainty))Source: wb_interface/rxreg_20 (FF)Destination: wb_interface/rxreg_20 (FF)Requirement: 10.000nsData Path Delay: 3.140ns (Levels of Logic = 1)Clock Path Skew: 0.000nsSource Clock: wb_clk_i_BUFGP falling at 5.000nsDestination Clock: wb_clk_i_BUFGP falling at 15.000nsClock Uncertainty: 0.000nsMaximum Data Path: wb_interface/rxreg_20 to wb_interface/rxreg_20Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X1Y54.XQ Tcko 0.591 wb_interface/rxreg<20>wb_interface/rxreg_20SLICE_X0Y54.G4 net (fanout=1) 0.404 wb_interface/rxreg<20>SLICE_X0Y54.Y Tilo 0.707 wb_interface/wb_dat_rdbkwb_interface/rxreg_and00001SLICE_X1Y54.CE net (fanout=2) 1.127 wb_interface/rxreg_and0000SLICE_X1Y54.CLK Tceck 0.311 wb_interface/rxreg<20>wb_interface/rxreg_20------------------------------------------------- ---------------------------Total 3.140ns (1.609ns logic, 1.531ns route)(51.2% logic, 48.8% route)--------------------------------------------------------------------------------Paths for end point wb_interface/rxreg_17 (SLICE_X1Y54.CE), 1 path--------------------------------------------------------------------------------Slack (setup path): 6.860ns (requirement - (data path - clock path skew + uncertainty))Source: wb_interface/rxreg_20 (FF)Destination: wb_interface/rxreg_17 (FF)Requirement: 10.000nsData Path Delay: 3.140ns (Levels of Logic = 1)Clock Path Skew: 0.000nsSource Clock: wb_clk_i_BUFGP falling at 5.000nsDestination Clock: wb_clk_i_BUFGP falling at 15.000nsClock Uncertainty: 0.000nsMaximum Data Path: wb_interface/rxreg_20 to wb_interface/rxreg_17Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X1Y54.XQ Tcko 0.591 wb_interface/rxreg<20>wb_interface/rxreg_20SLICE_X0Y54.G4 net (fanout=1) 0.404 wb_interface/rxreg<20>SLICE_X0Y54.Y Tilo 0.707 wb_interface/wb_dat_rdbkwb_interface/rxreg_and00001SLICE_X1Y54.CE net (fanout=2) 1.127 wb_interface/rxreg_and0000SLICE_X1Y54.CLK Tceck 0.311 wb_interface/rxreg<20>wb_interface/rxreg_17------------------------------------------------- ---------------------------Total 3.140ns (1.609ns logic, 1.531ns route)(51.2% logic, 48.8% route)--------------------------------------------------------------------------------Paths for end point wb_interface/rxreg_15 (SLICE_X1Y50.CE), 1 path--------------------------------------------------------------------------------Slack (setup path): 6.861ns (requirement - (data path - clock path skew + uncertainty))Source: wb_interface/rxreg_20 (FF)Destination: wb_interface/rxreg_15 (FF)Requirement: 10.000nsData Path Delay: 3.140ns (Levels of Logic = 1)Clock Path Skew: 0.001ns (0.020 - 0.019)Source Clock: wb_clk_i_BUFGP falling at 5.000nsDestination Clock: wb_clk_i_BUFGP falling at 15.000nsClock Uncertainty: 0.000nsMaximum Data Path: wb_interface/rxreg_20 to wb_interface/rxreg_15Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X1Y54.XQ Tcko 0.591 wb_interface/rxreg<20>wb_interface/rxreg_20SLICE_X0Y54.G4 net (fanout=1) 0.404 wb_interface/rxreg<20>SLICE_X0Y54.Y Tilo 0.707 wb_interface/wb_dat_rdbkwb_interface/rxreg_and00001SLICE_X1Y50.CE net (fanout=2) 1.127 wb_interface/rxreg_and0000SLICE_X1Y50.CLK Tceck 0.311 wb_interface/rxreg<15>wb_interface/rxreg_15------------------------------------------------- ---------------------------Total 3.140ns (1.609ns logic, 1.531ns route)(51.2% logic, 48.8% route)--------------------------------------------------------------------------------Hold Paths: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;--------------------------------------------------------------------------------Paths for end point wb_interface/txreg_20 (SLICE_X0Y56.CE), 1 path--------------------------------------------------------------------------------Slack (hold path): 1.912ns (requirement - (clock path skew + uncertainty - data path))Source: wb_interface/txreg_20 (FF)Destination: wb_interface/txreg_20 (FF)Requirement: 0.000nsData Path Delay: 1.912ns (Levels of Logic = 1)Clock Path Skew: 0.000nsSource Clock: wb_clk_i_BUFGP falling at 15.000nsDestination Clock: wb_clk_i_BUFGP falling at 15.000nsClock Uncertainty: 0.000nsMinimum Data Path: wb_interface/txreg_20 to wb_interface/txreg_20Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X0Y56.XQ Tcko 0.505 wb_interface/txreg<20>wb_interface/txreg_20SLICE_X1Y56.F1 net (fanout=1) 0.377 wb_interface/txreg<20>SLICE_X1Y56.X Tilo 0.514 wb_interface/txreg_and0000wb_interface/txreg_and00001SLICE_X0Y56.CE net (fanout=9) 0.516 wb_interface/txreg_and0000SLICE_X0Y56.CLK Tckce (-Th) 0.000 wb_interface/txreg<20>wb_interface/txreg_20------------------------------------------------- ---------------------------Total 1.912ns (1.019ns logic, 0.893ns route)(53.3% logic, 46.7% route)--------------------------------------------------------------------------------Paths for end point wb_interface/txreg_17 (SLICE_X0Y56.CE), 1 path--------------------------------------------------------------------------------Slack (hold path): 1.912ns (requirement - (clock path skew + uncertainty - data path))Source: wb_interface/txreg_20 (FF)Destination: wb_interface/txreg_17 (FF)Requirement: 0.000nsData Path Delay: 1.912ns (Levels of Logic = 1)Clock Path Skew: 0.000nsSource Clock: wb_clk_i_BUFGP falling at 15.000nsDestination Clock: wb_clk_i_BUFGP falling at 15.000nsClock Uncertainty: 0.000nsMinimum Data Path: wb_interface/txreg_20 to wb_interface/txreg_17Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X0Y56.XQ Tcko 0.505 wb_interface/txreg<20>wb_interface/txreg_20SLICE_X1Y56.F1 net (fanout=1) 0.377 wb_interface/txreg<20>SLICE_X1Y56.X Tilo 0.514 wb_interface/txreg_and0000wb_interface/txreg_and00001SLICE_X0Y56.CE net (fanout=9) 0.516 wb_interface/txreg_and0000SLICE_X0Y56.CLK Tckce (-Th) 0.000 wb_interface/txreg<20>wb_interface/txreg_17------------------------------------------------- ---------------------------Total 1.912ns (1.019ns logic, 0.893ns route)(53.3% logic, 46.7% route)--------------------------------------------------------------------------------Paths for end point wb_interface/txreg_5 (SLICE_X3Y47.CE), 1 path--------------------------------------------------------------------------------Slack (hold path): 1.944ns (requirement - (clock path skew + uncertainty - data path))Source: wb_interface/txreg_20 (FF)Destination: wb_interface/txreg_5 (FF)Requirement: 0.000nsData Path Delay: 2.094ns (Levels of Logic = 1)Clock Path Skew: 0.150ns (0.749 - 0.599)Source Clock: wb_clk_i_BUFGP falling at 15.000nsDestination Clock: wb_clk_i_BUFGP falling at 15.000nsClock Uncertainty: 0.000nsMinimum Data Path: wb_interface/txreg_20 to wb_interface/txreg_5Location Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X0Y56.XQ Tcko 0.505 wb_interface/txreg<20>wb_interface/txreg_20SLICE_X1Y56.F1 net (fanout=1) 0.377 wb_interface/txreg<20>SLICE_X1Y56.X Tilo 0.514 wb_interface/txreg_and0000wb_interface/txreg_and00001SLICE_X3Y47.CE net (fanout=9) 0.698 wb_interface/txreg_and0000SLICE_X3Y47.CLK Tckce (-Th) 0.000 wb_interface/txreg<5>wb_interface/txreg_5------------------------------------------------- ---------------------------Total 2.094ns (1.019ns logic, 1.075ns route)(48.7% logic, 51.3% route)--------------------------------------------------------------------------------Component Switching Limit Checks: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;--------------------------------------------------------------------------------Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))Period: 10.000nsLow pulse: 5.000nsLow pulse limit: 1.602ns (Trpw)Physical resource: wb_interface/txreg<1>/SRLogical resource: wb_interface/txreg_1/SRLocation pin: SLICE_X2Y51.SRClock network: wb_rst_i_IBUF--------------------------------------------------------------------------------Slack: 6.796ns (period - (min high pulse limit / (high pulse / period)))Period: 10.000nsHigh pulse: 5.000nsHigh pulse limit: 1.602ns (Trpw)Physical resource: wb_interface/txreg<1>/SRLogical resource: wb_interface/txreg_1/SRLocation pin: SLICE_X2Y51.SRClock network: wb_rst_i_IBUF--------------------------------------------------------------------------------Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))Period: 10.000nsLow pulse: 5.000nsLow pulse limit: 1.602ns (Trpw)Physical resource: wb_interface/txreg<1>/SRLogical resource: wb_interface/txreg_0/SRLocation pin: SLICE_X2Y51.SRClock network: wb_rst_i_IBUF--------------------------------------------------------------------------------All constraints were met.Data Sheet report:-----------------All values displayed in nanoseconds (ns)Clock to Setup on destination clock txclk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+txclk | 4.635| | | |---------------+---------+---------+---------+---------+Clock to Setup on destination clock wb_clk_i---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+wb_clk_i | | | | 3.140|---------------+---------+---------+---------+---------+Timing summary:---------------Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)Constraints cover 150 paths, 0 nets, and 140 connectionsDesign statistics:Minimum period: 4.635ns{1} (Maximum frequency: 215.750MHz)------------------------------------Footnotes-----------------------------------1) The minimum period statistic assumes all single cycle delays.Analysis completed Fri Feb 20 14:09:29 2015--------------------------------------------------------------------------------Trace Settings:-------------------------Trace SettingsPeak Memory Usage: 188 MB