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Release 14.7 Map P.20131013 (nt64)Xilinx Mapping Report File for Design 'sport_top'Design Information------------------Command Line : map -intstyle ise -p xc3s700an-fgg484-4 -cm area -ir off -proff -c 100 -o sport_top_map.ncd sport_top.ngd sport_top.pcfTarget Device : xc3s700anTarget Package : fgg484Target Speed : -4Mapper Version : spartan3a -- $Revision: 1.55 $Mapped Date : Fri Feb 20 14:08:41 2015Design Summary--------------Number of errors: 0Number of warnings: 2Logic Utilization:Number of Slice Flip Flops: 42 out of 11,776 1%Number of 4 input LUTs: 42 out of 11,776 1%Logic Distribution:Number of occupied Slices: 41 out of 5,888 1%Number of Slices containing only related logic: 41 out of 41 100%Number of Slices containing unrelated logic: 0 out of 41 0%*See NOTES below for an explanation of the effects of unrelated logic.Total Number of 4 input LUTs: 51 out of 11,776 1%Number used as logic: 42Number used as a route-thru: 9The Slice Logic Distribution report is not meaningful if the design isover-mapped for a non-slice resource or if Placement fails.Number of bonded IOBs: 76 out of 372 20%IOB Flip Flops: 2Number of BUFGMUXs: 3 out of 24 12%Average Fanout of Non-Clock Nets: 2.40Peak Memory Usage: 342 MBTotal REAL time to MAP completion: 15 secsTotal CPU time to MAP completion: 4 secsNOTES:Related logic is defined as being logic that shares connectivity - e.g. twoLUTs are "related" if they share common inputs. When assembling slices,Map gives priority to combine logic that is related. Doing so results inthe best timing performance.Unrelated logic shares no connectivity. Map will only begin packingunrelated logic into a slice once 99% of the slices are occupied throughrelated logic packing.Note that once logic distribution reaches the 99% level through relatedlogic packing, this does not mean the device is completely utilized.Unrelated logic packing will then begin, continuing until all usable LUTsand FFs are occupied. Depending on your timing budget, increased levels ofunrelated logic packing may adversely affect the overall timing performanceof your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Timing ReportSection 11 - Configuration String InformationSection 12 - Control Set InformationSection 13 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:PhysDesignRules:367 - The signal <DRxSEC_IBUF> is incomplete. The signaldoes not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <DRxPRI_IBUF> is incomplete. The signaldoes not drive any load pins in the design.Section 3 - Informational-------------------------INFO:LIT:243 - Logical network wb_dat_i<31> has no load.INFO:LIT:395 - The above info message is repeated 14 more times for thefollowing (max. 5 shown):wb_dat_i<30>,wb_dat_i<29>,wb_dat_i<28>,wb_dat_i<27>,wb_dat_i<26>To see the details of these info messages, please use the -detail switch.INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slewrate limited output drivers. The delay on speed critical single ended outputscan be dramatically reduced by designating them as fast outputs.Section 4 - Removed Logic Summary---------------------------------2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set thedetailed map report option and rerun map.Section 6 - IOB Properties--------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND || | | | | Term | Strength | Rate | | | Delay | |+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| DRxPRI | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || DRxSEC | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || DTxPRI | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || DTxSEC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || RFSx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || RSCLKx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || TFSx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || TSCLKx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || rx_int | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || rxclk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || txclk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_ack_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF1 | | 0 / 0 | 3STATE || wb_adr_i<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_adr_i<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_adr_i<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_adr_i<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_adr_i<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_adr_i<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_clk_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_cyc_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<8> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<9> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<10> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<11> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<12> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<13> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<14> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<15> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<16> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<17> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_i<20> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_dat_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<24> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<25> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<26> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<27> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<28> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<29> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<30> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_dat_o<31> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_err_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE || wb_rst_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_rty_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF1 | | 0 / 0 | 3STATE || wb_stb_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | || wb_we_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------Area Group Information----------------------No area groups were found in this design.----------------------Section 10 - Timing Report--------------------------This design was not run using timing mode.Section 11 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 12 - Control Set Information------------------------------------No control set information for this architecture.Section 13 - Utilization by Hierarchy-------------------------------------Use the "-detail" map option to print out the Utilization by Hierarchy section.